fix: incorrect settings of msi registers.
authorMinep <zelong56@gmail.com>
Tue, 9 Aug 2022 14:25:19 +0000 (15:25 +0100)
committerMinep <zelong56@gmail.com>
Tue, 9 Aug 2022 14:25:19 +0000 (15:25 +0100)
commit8b3a34da459067723ad288b2eb51a14473e0944f
tree908f34085b494041eca6d552167212d3a529c4a2
parente8e64a4f1d76aaeac3defa13243505cccd25c078
fix: incorrect settings of msi registers.
fix: enable correct hba interrupt for indicating end of transfer.
lunaix-os/hal/ahci/ahci.c
lunaix-os/hal/pci.c
lunaix-os/includes/hal/ahci/hba.h
lunaix-os/includes/hal/pci.h