1 #include <arch/x86/idt.h>
2 #include <arch/x86/interrupts.h>
7 uint64_t _idt[IDT_ENTRY];
8 uint16_t _idt_limit = sizeof(_idt) - 1;
10 static inline void _set_idt_entry(uint32_t vector, uint16_t seg_selector, void (*isr)(), uint8_t dpl, uint8_t type) {
11 uintptr_t offset = (uintptr_t)isr;
12 _idt[vector] = (offset & 0xffff0000) | IDT_ATTR(dpl, type);
14 _idt[vector] |= (seg_selector << 16) | (offset & 0x0000ffff);
17 void _set_idt_intr_entry(uint32_t vector, uint16_t seg_selector, void (*isr)(), uint8_t dpl) {
18 _set_idt_entry(vector, seg_selector, isr, dpl, IDT_INTERRUPT);
21 void _set_idt_trap_entry(uint32_t vector, uint16_t seg_selector, void (*isr)(), uint8_t dpl) {
22 _set_idt_entry(vector, seg_selector, isr, dpl, IDT_TRAP);
28 // CPU defined interrupts
29 _set_idt_intr_entry(FAULT_DIVISION_ERROR, 0x08, _asm_isr0, 0);
30 _set_idt_intr_entry(FAULT_GENERAL_PROTECTION, 0x08, _asm_isr13, 0);
31 _set_idt_intr_entry(FAULT_PAGE_FAULT, 0x08, _asm_isr14, 0);
33 _set_idt_intr_entry(APIC_ERROR_IV, 0x08, _asm_isr250, 0);
34 _set_idt_intr_entry(APIC_LINT0_IV, 0x08, _asm_isr251, 0);
35 _set_idt_intr_entry(APIC_SPIV_IV, 0x08, _asm_isr252, 0);
36 _set_idt_intr_entry(APIC_TIMER_IV, 0x08, _asm_isr253, 0);
37 _set_idt_intr_entry(PC_KBD_IV, 0x08, _asm_isr201, 0);
39 _set_idt_intr_entry(RTC_TIMER_IV, 0x08, _asm_isr210, 0);
41 // system defined interrupts
42 _set_idt_intr_entry(LUNAIX_SYS_PANIC, 0x08, _asm_isr32, 0);
44 // syscall is a trap gate (recall: trap does NOT clear IF flag upon interruption)
45 // XXX: this should be fine, as our design of context switch support interruptible syscall
46 // FIXME: This may cause nasty concurrency bug! We should 'lockify' our code!
47 _set_idt_trap_entry(LUNAIX_SYS_CALL, 0x08, _asm_isr33, 3);