4 #include <lunaix/device.h>
5 #include <lunaix/ds/ldga.h>
6 #include <lunaix/ds/llist.h>
7 #include <lunaix/types.h>
9 #define EXPORT_PCI_DEVICE(id, pci_devdef) \
10 EXPORT_DEVICE(id, &(pci_devdef)->devdef, load_pci_probe)
12 #define PCI_MATCH_EXACT -1
13 #define PCI_MATCH_ANY 0
14 #define PCI_MATCH_VENDOR 0xffff
17 #define PCI_TPCIBRIDGE 0x1
18 #define PCI_TCARDBRIDGE 0x2
20 #define PCI_VENDOR_INVLD 0xffff
22 #define PCI_REG_VENDOR_DEV 0
23 #define PCI_REG_STATUS_CMD 0x4
24 #define PCI_REG_BAR(num) (0x10 + (num - 1) * 4)
26 #define PCI_DEV_VENDOR(x) ((x) & 0xffff)
27 #define PCI_DEV_DEVID(x) (((x) & 0xffff0000) >> 16)
28 #define PCI_INTR_IRQ(x) ((x) & 0xff)
29 #define PCI_INTR_PIN(x) (((x) & 0xff00) >> 8)
30 #define PCI_DEV_CLASS(x) ((x) >> 8)
31 #define PCI_DEV_REV(x) (((x) & 0xff))
32 #define PCI_BUS_NUM(x) (((x) >> 16) & 0xff)
33 #define PCI_SLOT_NUM(x) (((x) >> 11) & 0x1f)
34 #define PCI_FUNCT_NUM(x) (((x) >> 8) & 0x7)
36 #define PCI_BAR_MMIO(x) (!((x) & 0x1))
37 #define PCI_BAR_CACHEABLE(x) ((x) & 0x8)
38 #define PCI_BAR_TYPE(x) ((x) & 0x6)
39 #define PCI_BAR_ADDR_MM(x) ((x) & ~0xf)
40 #define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)
42 #define PCI_MSI_ADDR(msi_base) ((msi_base) + 4)
43 #define PCI_MSI_DATA(msi_base, offset) ((msi_base) + 8 + offset)
44 #define PCI_MSI_MASK(msi_base, offset) ((msi_base) + 0xc + offset)
46 #define MSI_CAP_64BIT 0x80
47 #define MSI_CAP_MASK 0x100
48 #define MSI_CAP_ENABLE 0x1
50 #define PCI_RCMD_DISABLE_INTR (1 << 10)
51 #define PCI_RCMD_FAST_B2B (1 << 9)
52 #define PCI_RCMD_BUS_MASTER (1 << 2)
53 #define PCI_RCMD_MM_ACCESS (1 << 1)
54 #define PCI_RCMD_IO_ACCESS 1
56 #define PCI_ADDRESS(bus, dev, funct) \
57 (((bus) & 0xff) << 16) | (((dev) & 0xff) << 11) | \
58 (((funct) & 0xff) << 8) | 0x80000000
60 #define PCI_ID_ANY (-1)
62 typedef unsigned int pci_reg_t;
64 // PCI device header format
65 // Ref: "PCI Local Bus Specification, Rev.3, Section 6.1"
67 #define BAR_TYPE_MMIO 0x1
68 #define BAR_TYPE_CACHABLE 0x2
69 #define PCI_DRV_NAME_LEN 32
81 struct llist_header dev_chain;
87 struct pci_base_addr bar[6];
89 #define PCI_DEVICE(devbase) (container_of((devbase), struct pci_device, dev))
91 typedef void* (*pci_drv_init)(struct pci_device*);
93 #define PCI_DEVIDENT(vendor, id) \
94 ((((id) & 0xffff) << 16) | (((vendor) & 0xffff)))
101 struct device_def devdef;
105 * @brief 根据类型代码(Class Code)去在拓扑中寻找一个设备
106 * 类型代码请参阅: PCI LB Spec. Appendix D.
108 * @return struct pci_device*
110 struct pci_device* pci_get_device_by_class(u32_t class);
113 * @brief 根据设备商ID和设备ID,在拓扑中寻找一个设备
117 * @return struct pci_device*
120 pci_get_device_by_id(u16_t vendorId, u16_t deviceId);
123 * @brief 初始化PCI设备的基地址寄存器。返回由该基地址代表的,
124 * 设备所使用的MMIO或I/O地址空间的,大小。
125 * 参阅:PCI LB Spec. (Rev 3) Section 6.2.5.1, Implementation Note.
127 * @param dev The PCI device
128 * @param bar_out Value in BAR
129 * @param bar_num The index of BAR (starting from 1)
133 pci_bar_sizing(struct pci_device* dev, u32_t* bar_out, u32_t bar_num);
136 pci_add_driver(const char* name,
143 pci_bind_driver(struct pci_device* pci_dev);
146 pci_probe_bar_info(struct pci_device* device);
149 pci_probe_msi_info(struct pci_device* device);
151 #endif /* __LUNAIX_PCI_H */