lunaix-os/arch/aarch64/boot/init.c

   1 #include <lunaix/boot_generic.h>
   2 #include <sys/msrs.h>
   3
   4 #include "init.h"
   5
   6 static inline void
   7 setup_pstate()
   8 {
   9     /*
  10         SCTRL_EL1
  11             EE=0, E0E=0     // all little endian
  12             WXN=1           // write implie exec never
  13             SA0=1, SA=1     // alignment check on SP
  14             A=1             // alignment check on memref
  15             NMI=1           // mask interrupt
  16             M=1             // enable mmu
  17     */
  18
  19    unsigned long sctrl = 0;
  20
  21    sctrl |= SCTRL_NMI;
  22    sctrl |= SCTRL_WXN | SCTRL_nAA;
  23    sctrl |= SCTRL_SA | SCTRL_SA0;
  24    sctrl |= SCTRL_A | SCTRL_M;
  25
  26    set_sysreg(TCR_EL1, sctrl);
  27    set_sysreg(SPSel, 1);
  28 }
  29
  30 static inline void
  31 setup_evbar()
  32 {
  33     // TODO install exception vectors, setup VBAR
  34 }
  35
  36 static inline void
  37 setup_ttbr()
  38 {
  39     /*
  40
  41         TCR_EL1
  42             SH0=3           // Inner sharable
  43             ORGN0=0         // Normal memory, Outer Non-cacheable.
  44             IRGN0=1         // Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable.
  45             A1=0            // TTBR0 define ASID
  46             EPD1=0
  47             T1SZ=0
  48             EPD0=1
  49             T0SZ=16         // disable TTBR1, Use TTBR0 for all translation
  50             TG0=0           // VA48, 256T, 4K Granule
  51             TBI1=0,
  52             TBI0=0          // Ignore top bits
  53             AS=1            // 16bits asid
  54             HA=1
  55             HD=1            // Hardware managed dirty and access
  56
  57
  58         We may use the follow practice later
  59             TTBR0:  Translation for user-land (lowmem)
  60             TTBR1:  Translation for kernel-land (highmem)
  61     */
  62
  63     unsigned long tcr = 0;
  64     ptr_t ttb;
  65
  66     tcr |= TCR_T1SZ(0) | TCR_T0SZ(16);
  67     tcr |= TCR_TG0(TCR_G4K);
  68     tcr |= TCR_AS | TCR_HA | TCR_HD;
  69     tcr |= TCR_EPD0;
  70
  71     ttb = kremap();
  72
  73     set_sysreg(TTBR0_EL1, ttb);
  74     set_sysreg(TCR_EL1, tcr);
  75 }
  76
  77 static inline void
  78 extract_dtb_bootinfo(ptr_t dtb, struct boot_handoff* handoff)
  79 {
  80     handoff->kexec.dtb_pa = dtb;
  81
  82     // TODO extract /memory, /reserved-memories from dtb
  83 }
  84
  85 struct boot_handoff*
  86 aarch64_init(ptr_t dtb)
  87 {
  88     setup_evbar();
  89     setup_ttbr();
  90     setup_pstate();
  91
  92     struct boot_handoff* handoff;
  93
  94     handoff = bootmem_alloc(sizeof(*handoff));
  95
  96     extract_dtb_bootinfo(dtb, handoff);
  97
  98     return handoff;
  99 }