include("x86/LConfig")

@Collection("Platform")
def architecture_support():
    """
        Config ISA related features
    """

    @Term("Architecture")
    def arch():
        """ 
            Config ISA support 
        """
        # type(["i386", "x86_64", "aarch64", "rv64"])
        type(["i386", "x86_64", "aarch64"])
        default("x86_64")

        env_val = env("ARCH")
        if env_val:
            set_value(env_val)

    @Term("Base operand size")
    @ReadOnly
    def arch_bits():
        """ 
            Defines the base size of a general register of the 
            current selected ISA.

            This the 'bits' part when we are talking about a CPU
        """

        type(["64", "32"])
        match v(arch):
            case "i386": 
                default("32")
            case "aarch64": 
                default("64")
            case "rv64": 
                default("64")
            case "x86_64": 
                default("64")
            case _:
                default("32")