PCI 16x50 UART Controller, O2 Enablement (#39)

[lunaix-os.git] / lunaix-os / kernel / mm / mmio.c

diff --git a/lunaix-os/kernel/mm/mmio.c b/lunaix-os/kernel/mm/mmio.c
index 5e0d01e28601b321c94d62914e0d26b006715655..dbb1870afe9083437f7656d177fe579542184618 100644 (file)
--- a/lunaix-os/kernel/mm/mmio.c
+++ b/lunaix-os/kernel/mm/mmio.c
@@ -1,18 +1,26 @@
 #include <lunaix/mm/mmio.h>
 #include <lunaix/mm/mmio.h>

-#include <lunaix/mm/pmm.h>
-#include <lunaix/mm/vmm.h>
+#include <lunaix/mm/page.h>
+#include <lunaix/spike.h>

 
 

-void*
-ioremap(uintptr_t paddr, uint32_t size)
+ptr_t
+ioremap(ptr_t paddr, u32_t size)

 {
 {

-    return vmm_vmap(paddr, size, PG_PREM_RW | PG_DISABLE_CACHE);
+    // FIXME implement a page policy interface allow to decouple the 
+    //       arch-dependent caching behaviour
+
+    pfn_t start = pfn(paddr);
+    size_t npages = leaf_count(size);
+    
+    // Ensure the range is reservable (not already in use)
+    assert(pmm_onhold_range(start, npages));
+
+    ptr_t addr = vmap_range(start, npages, KERNEL_DATA);
+    return addr + va_offset(paddr);

 }
 
 }
 

-void*
-iounmap(uintptr_t vaddr, uint32_t size)
+void
+iounmap(ptr_t vaddr, u32_t size)

 {
 {

-    for (size_t i = 0; i < size; i += PG_SIZE) {
-        uintptr_t paddr = vmm_del_mapping(PD_REFERENCED, vaddr + i);
-        pmm_free_page(KERNEL_PID, paddr);
-    }
+    assert(vaddr >= VMAP && vaddr < VMAP_END);
+    vunmap_range(pfn(vaddr), leaf_count(size));

 }
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 }
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