add implementation of ARM GIC driver.

[lunaix-os.git] / lunaix-os / arch / LConfig

diff --git a/lunaix-os/arch/LConfig b/lunaix-os/arch/LConfig
index 30c67b626a5459780e8c85a446a920dba406ce25..10316363c2f09043a4a3e10ac59b5c2f71aa8594 100644 (file)
--- a/lunaix-os/arch/LConfig
+++ b/lunaix-os/arch/LConfig
@@ -1,13 +1,45 @@
-include("i386/LConfig")
+include("x86/LConfig")
+include("aarch64/LConfig")

 
 

-@Collection
+@Collection("Platform")

 def architecture_support():
     """
         Config ISA related features
     """
 
 def architecture_support():
     """
         Config ISA related features
     """
 

-    @Term
+    @Term("Architecture")

     def arch():
     def arch():

-        """ Config ISA support """
-        type(["i386", "x86_64", "aarch64", "rv64"])
-        default("i386")
+        """ 
+            Config ISA support 
+        """
+        # type(["i386", "x86_64", "aarch64", "rv64"])
+        type(["i386", "x86_64", "aarch64"])
+        default("x86_64")
+
+        env_val = env("ARCH")
+        if env_val:
+            set_value(env_val)
+
+    @Term("Base operand size")
+    @ReadOnly
+    def arch_bits():
+        """ 
+            Defines the base size of a general register of the 
+            current selected ISA.
+
+            This the 'bits' part when we are talking about a CPU
+        """
+
+        type(["64", "32"])
+        match v(arch):
+            case "i386": 
+                default("32")
+            case "aarch64": 
+                default("64")
+            case "rv64": 
+                default("64")
+            case "x86_64": 
+                default("64")
+            case _:
+                default("32")
+        
\ No newline at end of file