#include <lunaix/spike.h>
-#include <lunaix/owloysius.h>
-#include <asm-generic/isrm.h>
+#include <lunaix/device.h>
+#include <asm/x86_isrm.h>
#include "asm/x86.h"
#include "asm/soc/ioapic.h"
isrm_notify_eoi(id, LUNAIX_SCHED);
}
+msienv_t
+isrm_msi_start(struct device* dev)
+{
+ /*
+ * In x86, the MSI topology is rather simple, as the only
+ * source is the PCI itself, and the write destination is
+ * explictly defined in specification, so we don't need the
+ * msienv to hold dynamically probed address
+ */
+ return NULL;
+}
+
+int
+isrm_msi_avaliable(msienv_t msienv)
+{
+ return 1;
+}
+
+msi_vector_t
+isrm_msi_alloc(msienv_t msienv, cpu_t cpu, int index, isr_cb handler)
+{
+ unsigned int iv = isrm_ivexalloc(handler);
+
+ // we ignore the cpu redirection for now.
+ return (msi_vector_t){
+ .msi_addr = __APIC_BASE_PADDR,
+ .msi_data = iv,
+ .mapped_iv = iv
+ };
+}
+
+void
+isrm_msi_set_sideband(msienv_t msienv, ptr_t sideband)
+{
+ return;
+}
+
+void
+isrm_msi_done(msienv_t msienv)
+{
+ return;
+}
+
+
+
+int
+isrm_bind_dtn(struct dtn_intr* node)
+{
+ fail("not supported");
+}
-static void
-__intc_init()
+
+static int
+__intc_create(struct device_def* devdef, morph_t* obj)
{
apic_init();
ioapic_init();
arch_intc_ctx.name = "i386_apic";
arch_intc_ctx.irq_attach = ioapic_irq_remap;
arch_intc_ctx.notify_eoi = apic_on_eoi;
+
+ return 0;
}
-owloysius_fetch_init(__intc_init, on_earlyboot);
\ No newline at end of file
+
+
+static struct device_def i386_intc = {
+ def_device_class(INTEL, CFG, INTC),
+ def_device_name("i386 apic"),
+ def_on_create(__intc_create)
+};
+EXPORT_DEVICE(i386_intc, &i386_intc, load_sysconf);
\ No newline at end of file