feat: standard vga support (mode switching, framebuffer remapping)

[lunaix-os.git] / lunaix-os / kernel / mm / vmm.c

diff --git a/lunaix-os/kernel/mm/vmm.c b/lunaix-os/kernel/mm/vmm.c
index 3340f114c895ea05bc153aed0f52a9ac88589d2a..e21328f6c5f981d597de3371a133cf7b4c15e556 100644 (file)
--- a/lunaix-os/kernel/mm/vmm.c
+++ b/lunaix-os/kernel/mm/vmm.c
@@ -1,10 +1,12 @@
-#include <hal/cpu.h>
 #include <klibc/string.h>
 #include <lunaix/mm/pmm.h>
 #include <lunaix/mm/vmm.h>
 #include <lunaix/spike.h>
 #include <lunaix/syslog.h>
 
+#include <sys/cpu.h>
+#include <sys/mm/mempart.h>
+
 LOG_MODULE("VMM")
 
 void
@@ -41,7 +43,8 @@ vmm_set_mapping(ptr_t mnt, ptr_t va, ptr_t pa, pt_attr attr, int options)
     // See if attr make sense
     assert(attr <= 128);
 
-    if (!l1pt->entry[l1_inx]) {
+    x86_pte_t* l1pte = &l1pt->entry[l1_inx];
+    if (!*l1pte) {
         x86_page_table* new_l1pt_pa =
           (x86_page_table*)pmm_alloc_page(KERNEL_PID, PP_FGPERSIST);
 
@@ -51,14 +54,17 @@ vmm_set_mapping(ptr_t mnt, ptr_t va, ptr_t pa, pt_attr attr, int options)
         }
 
         // This must be writable
-        l1pt->entry[l1_inx] =
-          NEW_L1_ENTRY(attr | PG_WRITE | PG_PRESENT, new_l1pt_pa);
+        *l1pte = NEW_L1_ENTRY(attr | PG_WRITE | PG_PRESENT, new_l1pt_pa);
 
         // make sure our new l2 table is visible to CPU
-        cpu_invplg((ptr_t)l2pt);
+        cpu_flush_page((ptr_t)l2pt);
 
         memset((void*)l2pt, 0, PG_SIZE);
     } else {
+        if ((attr & PG_ALLOW_USER) && !(*l1pte & PG_ALLOW_USER)) {
+            *l1pte |= PG_ALLOW_USER;
+        }
+
         x86_pte_t pte = l2pt->entry[l2_inx];
         if (pte && (options & VMAP_IGNORE)) {
             return 1;
@@ -66,7 +72,7 @@ vmm_set_mapping(ptr_t mnt, ptr_t va, ptr_t pa, pt_attr attr, int options)
     }
 
     if (mnt == VMS_SELF) {
-        cpu_invplg(va);
+        cpu_flush_page(va);
     }
 
     if ((options & VMAP_NOMAP)) {
@@ -98,7 +104,7 @@ vmm_del_mapping(ptr_t mnt, ptr_t va)
         x86_page_table* l2pt = (x86_page_table*)(mnt | (l1_index << 12));
         x86_pte_t l2pte = l2pt->entry[l2_index];
 
-        cpu_invplg(va);
+        cpu_flush_page(va);
         l2pt->entry[l2_index] = PTE_NULL;
 
         return PG_ENTRY_ADDR(l2pte);
@@ -184,7 +190,7 @@ vmm_mount_pd(ptr_t mnt, ptr_t pde)
 {
     x86_page_table* l1pt = (x86_page_table*)L1_BASE_VADDR;
     l1pt->entry[(mnt >> 22)] = NEW_L1_ENTRY(T_SELF_REF_PERM, pde);
-    cpu_invplg(mnt);
+    cpu_flush_page(mnt);
     return mnt;
 }
 
@@ -193,6 +199,26 @@ vmm_unmount_pd(ptr_t mnt)
 {
     x86_page_table* l1pt = (x86_page_table*)L1_BASE_VADDR;
     l1pt->entry[(mnt >> 22)] = 0;
-    cpu_invplg(mnt);
+    cpu_flush_page(mnt);
     return mnt;
+}
+
+ptr_t
+vmm_dup_page(pid_t pid, ptr_t pa)
+{
+    ptr_t new_ppg = pmm_alloc_page(pid, 0);
+    vmm_set_mapping(VMS_SELF, PG_MOUNT_3, new_ppg, PG_PREM_RW, VMAP_NULL);
+    vmm_set_mapping(VMS_SELF, PG_MOUNT_4, pa, PG_PREM_RW, VMAP_NULL);
+
+    asm volatile("movl %1, %%edi\n"
+                 "movl %2, %%esi\n"
+                 "rep movsl\n" ::"c"(1024),
+                 "r"(PG_MOUNT_3),
+                 "r"(PG_MOUNT_4)
+                 : "memory", "%edi", "%esi");
+
+    vmm_del_mapping(VMS_SELF, PG_MOUNT_3);
+    vmm_del_mapping(VMS_SELF, PG_MOUNT_4);
+
+    return new_ppg;
 }
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