feat: MSI capability detection.

[lunaix-os.git] / lunaix-os / includes / hal / pci.h

diff --git a/lunaix-os/includes/hal/pci.h b/lunaix-os/includes/hal/pci.h
index 3e421ee76803e1fdb5d7ea94a8d16ae90ee9e16b..bd203590100e8c48e8b473fbb47d7ecc295efc31 100644 (file)
--- a/lunaix-os/includes/hal/pci.h
+++ b/lunaix-os/includes/hal/pci.h
@@ -13,13 +13,23 @@
 
 #define PCI_VENDOR_INVLD 0xffff
 
 
 #define PCI_VENDOR_INVLD 0xffff
 

-#define PCI_REG_VENDER 0x0
-#define PCI_REG_DEV 0x1
-#define PCI_REG_HDRTYPE 0x7
-
-#define PCI_ADDRESS(bus, dev, funct, reg)                                      \
+#define PCI_REG_VENDOR_DEV 0
+#define PCI_REG_STATUS_CMD 0x4
+#define PCI_REG_BAR(offset) (0x10 + (offset)*4)
+
+#define PCI_DEV_VENDOR(x) ((x)&0xffff)
+#define PCI_DEV_DEVID(x) ((x) >> 16)
+#define PCI_INTR_IRQ(x) ((x)&0xff)
+#define PCI_INTR_PIN(x) (((x)&0xff00) >> 8)
+#define PCI_DEV_CLASS(x) ((x) >> 8)
+#define PCI_DEV_REV(x) (((x)&0xff))
+#define PCI_BUS_NUM(x) ((x >> 16) & 0xff)
+#define PCI_SLOT_NUM(x) ((x >> 11) & 0x1f)
+#define PCI_FUNCT_NUM(x) ((x >> 8) & 0x7)
+
+#define PCI_ADDRESS(bus, dev, funct)                                           \

     (((bus)&0xff) << 16) | (((dev)&0xff) << 11) | (((funct)&0xff) << 8) |      \
     (((bus)&0xff) << 16) | (((dev)&0xff) << 11) | (((funct)&0xff) << 8) |      \

-      (((reg)&0xff) << 2) | 0x80000000
+      0x80000000

 
 typedef unsigned int pci_reg_t;
 
 
 typedef unsigned int pci_reg_t;
 


@@ -29,32 +39,27 @@ typedef unsigned int pci_reg_t;
 struct pci_device
 {
     struct llist_header dev_chain;
 struct pci_device
 {
     struct llist_header dev_chain;

-    uint16_t vendor;
-    uint16_t deviceId;
-    uint32_t class_code;
-    uint8_t bus;
-    uint8_t dev;
-    uint8_t function;
-    uint8_t type;
-    uint8_t intr_line;
-    uint8_t intr_pintype;
-    uint32_t bars[6];
+    uint32_t device_info;
+    uint32_t class_info;
+    uint32_t cspace_base;
+    uint32_t msi_loc;
+    uint16_t intr_info;

 };
 
 // PCI Configuration Space (C-Space) r/w:
 //      Refer to "PCI Local Bus Specification, Rev.3, Section 3.2.2.3.2"
 
 inline pci_reg_t
 };
 
 // PCI Configuration Space (C-Space) r/w:
 //      Refer to "PCI Local Bus Specification, Rev.3, Section 3.2.2.3.2"
 
 inline pci_reg_t

-pci_read_cspace(int bus, int dev, int funct, int reg)
+pci_read_cspace(uint32_t base, int offset)

 {
 {

-    io_outl(PCI_CONFIG_ADDR, PCI_ADDRESS(bus, dev, funct, reg));
+    io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));

     return io_inl(PCI_CONFIG_DATA);
 }
 
 inline void
     return io_inl(PCI_CONFIG_DATA);
 }
 
 inline void

-pci_write_cspace(int bus, int dev, int funct, int reg, pci_reg_t data)
+pci_write_cspace(uint32_t base, int offset, pci_reg_t data)

 {
 {

-    io_outl(PCI_CONFIG_ADDR, PCI_ADDRESS(bus, dev, funct, reg));
+    io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));

     io_outl(PCI_CONFIG_DATA, data);
 }
 
     io_outl(PCI_CONFIG_DATA, data);
 }
 


@@ -67,7 +72,9 @@ pci_init();
 void
 pci_print_device();
 
 void
 pci_print_device();
 

+struct pci_device* pci_get_device_by_class(uint32_t class);
+

 struct pci_device*
 struct pci_device*

-pci_get_device(uint16_t vendorId, uint16_t deviceId);
+pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId);

 
 #endif /* __LUNAIX_PCI_H */
 
 #endif /* __LUNAIX_PCI_H */