feat: a file system mapping for pci devices

[lunaix-os.git] / lunaix-os / hal / pci.c

diff --git a/lunaix-os/hal/pci.c b/lunaix-os/hal/pci.c
index 8bc35cee55cbdd56a5422b2462304c57b6f3a2a9..ca31e21c7656d05eddd6a9931429a588c3fe0cb4 100644 (file)
--- a/lunaix-os/hal/pci.c
+++ b/lunaix-os/hal/pci.c
@@ -1,27 +1,46 @@
+/**
+ * @file pci.c
+ * @author Lunaixsky (zelong56@gmail.com)
+ * @brief A software implementation of PCI Local Bus Specification Revision 3.0
+ * @version 0.1
+ * @date 2022-06-28
+ *
+ * @copyright Copyright (c) 2022
+ *
+ */
+#include <hal/acpi/acpi.h>
+#include <hal/apic.h>

 #include <hal/pci.h>
 #include <hal/pci.h>

-#include <lunaix/mm/kalloc.h>
+#include <lunaix/fs/twifs.h>
+#include <lunaix/mm/valloc.h>
+#include <lunaix/spike.h>

 #include <lunaix/syslog.h>
 
 LOG_MODULE("PCI")
 
 static struct llist_header pci_devices;
 
 #include <lunaix/syslog.h>
 
 LOG_MODULE("PCI")
 
 static struct llist_header pci_devices;
 

+void
+pci_probe_msi_info(struct pci_device* device);
+

 void
 pci_probe_device(int bus, int dev, int funct)
 {
 void
 pci_probe_device(int bus, int dev, int funct)
 {

-    pci_reg_t reg1 = pci_read_cspace(bus, dev, funct, 0);
-    uint32_t vendor = reg1 & 0xffff;
-    pci_reg_t dev_id = reg1 >> 16;
+    uint32_t base = PCI_ADDRESS(bus, dev, funct);
+    pci_reg_t reg1 = pci_read_cspace(base, 0);

 
     // Vendor=0xffff则表示设备不存在
 
     // Vendor=0xffff则表示设备不存在

-    if (vendor == PCI_VENDOR_INVLD) {
+    if (PCI_DEV_VENDOR(reg1) == PCI_VENDOR_INVLD) {

         return;
     }
 
         return;
     }
 

-    pci_reg_t hdr_type = pci_read_cspace(bus, dev, funct, 3);
+    pci_reg_t hdr_type = pci_read_cspace(base, 0xc);

     hdr_type = (hdr_type >> 16) & 0xff;
 
     hdr_type = (hdr_type >> 16) & 0xff;
 

-    if ((hdr_type & 0x80)) {
+    // 防止堆栈溢出
+    // QEMU的ICH9/Q35实现似乎有点问题，对于多功能设备的每一个功能的header type
+    //  都将第七位置位。而virtualbox 就没有这个毛病。
+    if ((hdr_type & 0x80) && funct == 0) {

         hdr_type = hdr_type & ~0x80;
         // 探测多用途设备（multi-function device）
         for (int i = 1; i < 7; i++) {
         hdr_type = hdr_type & ~0x80;
         // 探测多用途设备（multi-function device）
         for (int i = 1; i < 7; i++) {


@@ -29,29 +48,21 @@ pci_probe_device(int bus, int dev, int funct)
         }
     }
 
         }
     }
 

-    if (hdr_type != 0) {
+    if (hdr_type != PCI_TDEV) {

         // XXX: 目前忽略所有桥接设备，比如PCI-PCI桥接器，或者是CardBus桥接器
         return;
     }
 
         // XXX: 目前忽略所有桥接设备，比如PCI-PCI桥接器，或者是CardBus桥接器
         return;
     }
 

-    pci_reg_t intr = pci_read_cspace(bus, dev, funct, 15);
-    pci_reg_t class = pci_read_cspace(bus, dev, funct, 2) >> 8;
-
-    struct pci_device* device = lxmalloc(sizeof(struct pci_device));
-    *device = (struct pci_device){ .bus = bus,
-                                   .dev = dev,
-                                   .function = funct,
-                                   .class_code = class,
-                                   .vendor = vendor,
-                                   .deviceId = dev_id,
-                                   .type = hdr_type,
-                                   .intr_line = intr & 0xff,
-                                   .intr_pintype = (intr >> 8) & 0xff };
-
-    // 读取设备的内存映射的寄存器的基地址
-    for (int i = 0; i < 6; i++) {
-        device->bars[i] = pci_read_cspace(bus, dev, funct, 4 + i);
-    }
+    pci_reg_t intr = pci_read_cspace(base, 0x3c);
+    pci_reg_t class = pci_read_cspace(base, 0x8);
+
+    struct pci_device* device = valloc(sizeof(struct pci_device));
+    *device = (struct pci_device){ .cspace_base = base,
+                                   .class_info = class,
+                                   .device_info = reg1,
+                                   .intr_info = intr };
+
+    pci_probe_msi_info(device);

 
     llist_append(&pci_devices, &device->dev_chain);
 }
 
     llist_append(&pci_devices, &device->dev_chain);
 }


@@ -69,34 +80,144 @@ pci_probe()
 }
 
 void
 }
 
 void

-pci_print_device()
+pci_probe_msi_info(struct pci_device* device)
+{
+    // Note that Virtualbox have to use ICH9 chipset for MSI support.
+    // Qemu seems ok with default PIIX3, Bochs is pending to test...
+    //    See https://www.virtualbox.org/manual/ch03.html (section 3.5.1)
+    pci_reg_t status =
+      pci_read_cspace(device->cspace_base, PCI_REG_STATUS_CMD) >> 16;
+
+    if (!(status & 0x10)) {
+        device->msi_loc = 0;
+        return;
+    }
+
+    pci_reg_t cap_ptr = pci_read_cspace(device->cspace_base, 0x34) & 0xff;
+    uint32_t cap_hdr;
+
+    while (cap_ptr) {
+        cap_hdr = pci_read_cspace(device->cspace_base, cap_ptr);
+        if ((cap_hdr & 0xff) == 0x5) {
+            // MSI
+            device->msi_loc = cap_ptr;
+            return;
+        }
+        cap_ptr = (cap_hdr >> 8) & 0xff;
+    }
+}
+
+#define PCI_PRINT_BAR_LISTING
+
+int
+__pci_read_cspace(struct v_inode* inode, void* buffer, size_t len, size_t fpos)
+{
+    if (len < 256) {
+        return ERANGE;
+    }
+
+    struct twifs_node* node = (struct twifs_node*)(inode->data);
+    struct pci_device* pcidev = (struct pci_device*)(node->data);
+
+    for (size_t i = 0; i < 256; i += sizeof(pci_reg_t)) {
+        *(pci_reg_t*)(buffer + i) = pci_read_cspace(pcidev->cspace_base, i);
+    }
+
+    return 256;
+}
+
+void
+pci_build_fsmapping()
+{
+    struct twifs_node *pci_class = twifs_dir_node(NULL, "pci"), *pci_dev;
+    struct pci_device *pos, *n;
+    llist_for_each(pos, n, &pci_devices, dev_chain)
+    {
+        pci_dev = twifs_dir_node(pci_class,
+                                 "B%d:D%d:F%d.%x:%x",
+                                 PCI_BUS_NUM(pos->cspace_base),
+                                 PCI_SLOT_NUM(pos->cspace_base),
+                                 PCI_FUNCT_NUM(pos->cspace_base),
+                                 PCI_DEV_VENDOR(pos->device_info),
+                                 PCI_DEV_DEVID(pos->device_info));
+        struct twifs_node* fnode = twifs_file_node(pci_dev, "cspace");
+        fnode->data = pos;
+        fnode->ops.read = __pci_read_cspace;
+    }
+}
+
+size_t
+pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num)
+{
+    pci_reg_t bar = pci_read_cspace(dev->cspace_base, PCI_REG_BAR(bar_num));
+    if (!bar) {
+        *bar_out = 0;
+        return 0;
+    }
+
+    pci_write_cspace(dev->cspace_base, PCI_REG_BAR(bar_num), 0xffffffff);
+    pci_reg_t sized =
+      pci_read_cspace(dev->cspace_base, PCI_REG_BAR(bar_num)) & ~0x1;
+    if (PCI_BAR_MMIO(bar)) {
+        sized = PCI_BAR_ADDR_MM(sized);
+    }
+    *bar_out = bar;
+    pci_write_cspace(dev->cspace_base, PCI_REG_BAR(bar_num), bar);
+    return ~sized + 1;
+}
+
+void
+pci_setup_msi(struct pci_device* device, int vector)

 {
 {

+    // Dest: APIC#0, Physical Destination, No redirection
+    uint32_t msi_addr = (__APIC_BASE_PADDR);
+
+    // Edge trigger, Fixed delivery
+    uint32_t msi_data = vector;
+
+    pci_write_cspace(
+      device->cspace_base, PCI_MSI_ADDR(device->msi_loc), msi_addr);
+
+    pci_reg_t reg1 = pci_read_cspace(device->cspace_base, device->msi_loc);
+    pci_reg_t msg_ctl = reg1 >> 16;
+
+    int offset = !!(msg_ctl & MSI_CAP_64BIT) * 4;
+    pci_write_cspace(device->cspace_base,
+                     PCI_MSI_DATA(device->msi_loc, offset),
+                     msi_data & 0xffff);
+
+    if ((msg_ctl & MSI_CAP_MASK)) {
+        pci_write_cspace(
+          device->cspace_base, PCI_MSI_MASK(device->msi_loc, offset), 0);
+    }
+
+    // manipulate the MSI_CTRL to allow device using MSI to request service.
+    reg1 = (reg1 & 0xff8fffff) | 0x10000;
+    pci_write_cspace(device->cspace_base, device->msi_loc, reg1);
+}
+
+struct pci_device*
+pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId)
+{
+    uint32_t dev_info = vendorId | (deviceId << 16);

     struct pci_device *pos, *n;
     llist_for_each(pos, n, &pci_devices, dev_chain)
     {
     struct pci_device *pos, *n;
     llist_for_each(pos, n, &pci_devices, dev_chain)
     {

-        kprintf(KINFO "(B%xh:D%xh:F%xh) Dev %x:%x, Class 0x%x\n",
-                pos->bus,
-                pos->dev,
-                pos->function,
-                pos->vendor,
-                pos->deviceId,
-                pos->class_code);
-
-        for (int i = 0; i < 6; i++) {
-            kprintf(KINFO "\t BAR#%d: %p\n", i, pos->bars[i]);
+        if (pos->device_info == dev_info) {
+            return pos;

         }
         }

-        kprintf(
-          KINFO "\t IRQ: %d, INT#x: %d\n\n", pos->intr_line, pos->intr_pintype);

     }
     }

+
+    return NULL;

 }
 
 struct pci_device*
 }
 
 struct pci_device*

-pci_get_device(uint16_t vendorId, uint16_t deviceId)
+pci_get_device_by_class(uint32_t class)

 {
     struct pci_device *pos, *n;
     llist_for_each(pos, n, &pci_devices, dev_chain)
     {
 {
     struct pci_device *pos, *n;
     llist_for_each(pos, n, &pci_devices, dev_chain)
     {

-        if (pos->vendor == vendorId && pos->deviceId == deviceId) {
+        if (PCI_DEV_CLASS(pos->class_info) == class) {

             return pos;
         }
     }
             return pos;
         }
     }


@@ -108,5 +229,14 @@ void
 pci_init()
 {
     llist_init_head(&pci_devices);
 pci_init()
 {
     llist_init_head(&pci_devices);

+    acpi_context* acpi = acpi_get_context();
+    assert_msg(acpi, "ACPI not initialized.");
+    if (acpi->mcfg.alloc_num) {
+        // PCIe Enhanced Configuration Mechanism is supported.
+        // TODO: support PCIe addressing mechanism
+    }
+    // Otherwise, fallback to use legacy PCI 3.0 method.

     pci_probe();
     pci_probe();

+
+    pci_build_fsmapping();

 }
\ No newline at end of file
 }
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