#define PCI_REG_STATUS_CMD 0x4
#define PCI_REG_BAR(num) (0x10 + (num - 1) * 4)
-#define PCI_DEV_VENDOR(x) ((x)&0xffff)
-#define PCI_DEV_DEVID(x) (((x)&0xffff0000) >> 16)
-#define PCI_INTR_IRQ(x) ((x)&0xff)
-#define PCI_INTR_PIN(x) (((x)&0xff00) >> 8)
+#define PCI_DEV_VENDOR(x) ((x) & 0xffff)
+#define PCI_DEV_DEVID(x) (((x) & 0xffff0000) >> 16)
+#define PCI_INTR_IRQ(x) ((x) & 0xff)
+#define PCI_INTR_PIN(x) (((x) & 0xff00) >> 8)
#define PCI_DEV_CLASS(x) ((x) >> 8)
-#define PCI_DEV_REV(x) (((x)&0xff))
+#define PCI_DEV_REV(x) (((x) & 0xff))
#define PCI_BUS_NUM(x) (((x) >> 16) & 0xff)
#define PCI_SLOT_NUM(x) (((x) >> 11) & 0x1f)
#define PCI_FUNCT_NUM(x) (((x) >> 8) & 0x7)
-#define PCI_BAR_MMIO(x) (!((x)&0x1))
-#define PCI_BAR_CACHEABLE(x) ((x)&0x8)
-#define PCI_BAR_TYPE(x) ((x)&0x6)
+#define PCI_BAR_MMIO(x) (!((x) & 0x1))
+#define PCI_BAR_CACHEABLE(x) ((x) & 0x8)
+#define PCI_BAR_TYPE(x) ((x) & 0x6)
#define PCI_BAR_ADDR_MM(x) ((x) & ~0xf)
#define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)
#define PCI_RCMD_IO_ACCESS 1
#define PCI_ADDRESS(bus, dev, funct) \
- (((bus)&0xff) << 16) | (((dev)&0xff) << 11) | (((funct)&0xff) << 8) | \
- 0x80000000
+ (((bus) & 0xff) << 16) | (((dev) & 0xff) << 11) | \
+ (((funct) & 0xff) << 8) | 0x80000000
#define PCI_ID_ANY (-1)
u16_t intr_info;
struct pci_base_addr bar[6];
};
+#define PCI_DEVICE(devbase) (container_of((devbase), struct pci_device, dev))
typedef void* (*pci_drv_init)(struct pci_device*);
+#define PCI_DEVIDENT(vendor, id) \
+ ((((id) & 0xffff) << 16) | (((vendor) & 0xffff)))
+
struct pci_device_def
{
u32_t dev_class;
- u32_t dev_vendor;
- u32_t dev_id;
+ u32_t dev_ident;
+ u32_t ident_mask;
struct device_def devdef;
};