refactor: striped more arch-related code from the kernel code base

[lunaix-os.git] / lunaix-os / hal / ioapic.c

diff --git a/lunaix-os/hal/ioapic.c b/lunaix-os/hal/ioapic.c
index dbe910612aaf8718a6a0cc8bce72aa86cb0309cf..f0bd706a1aed4b41f1ff22e7256bbbc7786476f4 100644 (file)
--- a/lunaix-os/hal/ioapic.c
+++ b/lunaix-os/hal/ioapic.c
@@ -1,13 +1,13 @@
-#include <arch/x86/interrupts.h>
+#include <sys/interrupts.h>
 #include <hal/acpi/acpi.h>
 #include <hal/ioapic.h>
 #include <lunaix/common.h>
+#include <lunaix/mm/mmio.h>
 
-#define IOAPIC_REG_SEL *((volatile uint32_t*)(MMIO_IOAPIC + IOAPIC_IOREGSEL))
-#define IOAPIC_REG_WIN *((volatile uint32_t*)(MMIO_IOAPIC + IOAPIC_IOWIN))
+#define IOAPIC_REG_SEL *((volatile u32_t*)(_ioapic_base + IOAPIC_IOREGSEL))
+#define IOAPIC_REG_WIN *((volatile u32_t*)(_ioapic_base + IOAPIC_IOWIN))
 
-uint8_t
-ioapic_get_irq(acpi_context* acpi_ctx, uint8_t old_irq);
+static volatile ptr_t _ioapic_base;
 
 void
 ioapic_init()
@@ -16,50 +16,28 @@ ioapic_init()
 
     acpi_context* acpi_ctx = acpi_get_context();
 
-    // Remap the IRQ 8 (rtc timer's vector) to RTC_TIMER_IV in ioapic
-    //       (Remarks IRQ 8 is pin INTIN8)
-    //       See IBM PC/AT Technical Reference 1-10 for old RTC IRQ
-    //       See Intel's Multiprocessor Specification for IRQ - IOAPIC INTIN
-    //       mapping config.
-
-    // The ioapic_get_irq is to make sure we capture those overriden IRQs
-
-    // grab ourselves these irq numbers
-    uint8_t irq_rtc = ioapic_get_irq(acpi_ctx, PC_AT_IRQ_RTC);
-
-    // PC_AT_IRQ_RTC -> RTC_TIMER_IV, fixed, edge trigged, polarity=high,
-    // physical, APIC ID 0
-    ioapic_redirect(irq_rtc, RTC_TIMER_IV, 0, IOAPIC_DELMOD_FIXED);
-}
-
-uint8_t
-ioapic_get_irq(acpi_context* acpi_ctx, uint8_t old_irq)
-{
-    if (old_irq >= 24) {
-        return old_irq;
-    }
-    acpi_intso_t* int_override = acpi_ctx->madt.irq_exception[old_irq];
-    return int_override ? (uint8_t)int_override->gsi : old_irq;
+    _ioapic_base =
+      (ptr_t)ioremap(acpi_ctx->madt.ioapic->ioapic_addr & ~0xfff, 4096);
 }
 
 void
-ioapic_write(uint8_t sel, uint32_t val)
+ioapic_write(u8_t sel, u32_t val)
 {
     IOAPIC_REG_SEL = sel;
     IOAPIC_REG_WIN = val;
 }
 
-uint32_t
-ioapic_read(uint8_t sel)
+u32_t
+ioapic_read(u8_t sel)
 {
     IOAPIC_REG_SEL = sel;
     return IOAPIC_REG_WIN;
 }
 
 void
-ioapic_redirect(uint8_t irq, uint8_t vector, uint8_t dest, uint32_t flags)
+ioapic_redirect(u8_t irq, u8_t vector, u8_t dest, u32_t flags)
 {
-    uint8_t reg_sel = IOAPIC_IOREDTBL_BASE + irq * 2;
+    u8_t reg_sel = IOAPIC_IOREDTBL_BASE + irq * 2;
 
     // Write low 32 bits
     ioapic_write(reg_sel, (vector | flags) & 0x1FFFF);