fix: the correct way to detect ahci LBA48 support

[lunaix-os.git] / lunaix-os / kernel / time / timer.c

diff --git a/lunaix-os/kernel/time/timer.c b/lunaix-os/kernel/time/timer.c
index b9d333b1273856d202d2db4a0625e6cb9948654e..d99aac49dafc211f8fb9bf9fd2465e4bc1a0c1eb 100644 (file)
--- a/lunaix-os/kernel/time/timer.c
+++ b/lunaix-os/kernel/time/timer.c
@@ -13,12 +13,16 @@
 #include <hal/apic.h>
 #include <hal/rtc.h>
 
-#include <lunaix/mm/kalloc.h>
+#include <lunaix/isrm.h>
+#include <lunaix/mm/cake.h>
+#include <lunaix/mm/valloc.h>
 #include <lunaix/sched.h>
 #include <lunaix/spike.h>
 #include <lunaix/syslog.h>
 #include <lunaix/timer.h>
 
+#include <hal/acpi/acpi.h>
+
 #define LVT_ENTRY_TIMER(vector, mode) (LVT_DELIVERY_FIXED | mode | vector)
 
 LOG_MODULE("TIMER");
@@ -36,29 +40,31 @@ static volatile struct lx_timer_context* timer_ctx = NULL;
 
 // Don't optimize them! Took me an half hour to figure that out...
 
-static volatile uint32_t rtc_counter = 0;
+static volatile u32_t rtc_counter = 0;
 static volatile uint8_t apic_timer_done = 0;
 
-static volatile uint32_t sched_ticks = 0;
-static volatile uint32_t sched_ticks_counter = 0;
+static volatile u32_t sched_ticks = 0;
+static volatile u32_t sched_ticks_counter = 0;
+
+static struct cake_pile* timer_pile;
 
 #define APIC_CALIBRATION_CONST 0x100000
 
 void
 timer_init_context()
 {
+    timer_pile = cake_new_pile("timer", sizeof(struct lx_timer), 1, 0);
     timer_ctx =
-      (struct lx_timer_context*)lxmalloc(sizeof(struct lx_timer_context));
+      (struct lx_timer_context*)valloc(sizeof(struct lx_timer_context));
 
     assert_msg(timer_ctx, "Fail to initialize timer contex");
 
-    timer_ctx->active_timers =
-      (struct lx_timer*)lxmalloc(sizeof(struct lx_timer));
-    llist_init_head(timer_ctx->active_timers);
+    timer_ctx->active_timers = (struct lx_timer*)cake_grab(timer_pile);
+    llist_init_head(&timer_ctx->active_timers->link);
 }
 
 void
-timer_init(uint32_t frequency)
+timer_init(u32_t frequency)
 {
     timer_init_context();
 
@@ -66,10 +72,20 @@ timer_init(uint32_t frequency)
 
     // Setup APIC timer
 
+    // Remap the IRQ 8 (rtc timer's vector) to RTC_TIMER_IV in ioapic
+    //       (Remarks IRQ 8 is pin INTIN8)
+    //       See IBM PC/AT Technical Reference 1-10 for old RTC IRQ
+    //       See Intel's Multiprocessor Specification for IRQ - IOAPIC INTIN
+    //       mapping config.
+
+    // grab ourselves these irq numbers
+    u32_t iv_rtc = isrm_bindirq(PC_AT_IRQ_RTC, temp_intr_routine_rtc_tick);
+    u32_t iv_timer = isrm_ivexalloc(temp_intr_routine_apic_timer);
+
     // Setup a one-shot timer, we will use this to measure the bus speed. So we
     // can then calibrate apic timer to work at *nearly* accurate hz
     apic_write_reg(APIC_TIMER_LVT,
-                   LVT_ENTRY_TIMER(APIC_TIMER_IV, LVT_TIMER_ONESHOT));
+                   LVT_ENTRY_TIMER(iv_timer, LVT_TIMER_ONESHOT));
 
     // Set divider to 64
     apic_write_reg(APIC_TIMER_DCR, APIC_TIMER_DIV64);
@@ -107,9 +123,6 @@ timer_init(uint32_t frequency)
     rtc_counter = 0;
     apic_timer_done = 0;
 
-    intr_subscribe(APIC_TIMER_IV, temp_intr_routine_apic_timer);
-    intr_subscribe(RTC_TIMER_IV, temp_intr_routine_rtc_tick);
-
     rtc_enable_timer();                                     // start RTC timer
     apic_write_reg(APIC_TIMER_ICR, APIC_CALIBRATION_CONST); // start APIC timer
 
@@ -120,18 +133,19 @@ timer_init(uint32_t frequency)
 
     assert_msg(timer_ctx->base_frequency, "Fail to initialize timer (NOFREQ)");
 
-    kprintf(KINFO "Base frequency: %u Hz\n", timer_ctx->base_frequency);
+    kprintf(
+      KINFO "hw: %u Hz; os: %u Hz\n", timer_ctx->base_frequency, frequency);
 
     timer_ctx->running_frequency = frequency;
     timer_ctx->tphz = timer_ctx->base_frequency / frequency;
 
     // cleanup
-    intr_unsubscribe(APIC_TIMER_IV, temp_intr_routine_apic_timer);
-    intr_unsubscribe(RTC_TIMER_IV, temp_intr_routine_rtc_tick);
+    isrm_ivfree(iv_timer);
+    isrm_ivfree(iv_rtc);
 
-    apic_write_reg(APIC_TIMER_LVT,
-                   LVT_ENTRY_TIMER(APIC_TIMER_IV, LVT_TIMER_PERIODIC));
-    intr_subscribe(APIC_TIMER_IV, timer_update);
+    apic_write_reg(
+      APIC_TIMER_LVT,
+      LVT_ENTRY_TIMER(isrm_ivexalloc(timer_update), LVT_TIMER_PERIODIC));
 
     apic_write_reg(APIC_TIMER_ICR, timer_ctx->tphz);
 
@@ -140,7 +154,7 @@ timer_init(uint32_t frequency)
 }
 
 struct lx_timer*
-timer_run_second(uint32_t second,
+timer_run_second(u32_t second,
                  void (*callback)(void*),
                  void* payload,
                  uint8_t flags)
@@ -150,7 +164,7 @@ timer_run_second(uint32_t second,
 }
 
 struct lx_timer*
-timer_run_ms(uint32_t millisecond,
+timer_run_ms(u32_t millisecond,
              void (*callback)(void*),
              void* payload,
              uint8_t flags)
@@ -164,8 +178,7 @@ timer_run_ms(uint32_t millisecond,
 struct lx_timer*
 timer_run(ticks_t ticks, void (*callback)(void*), void* payload, uint8_t flags)
 {
-    struct lx_timer* timer =
-      (struct lx_timer*)lxmalloc(sizeof(struct lx_timer));
+    struct lx_timer* timer = (struct lx_timer*)cake_grab(timer_pile);
 
     if (!timer)
         return NULL;
@@ -176,7 +189,7 @@ timer_run(ticks_t ticks, void (*callback)(void*), void* payload, uint8_t flags)
     timer->payload = payload;
     timer->flags = flags;
 
-    llist_append(timer_ctx->active_timers, &timer->link);
+    llist_append(&timer_ctx->active_timers->link, &timer->link);
 
     return timer;
 }
@@ -199,7 +212,7 @@ timer_update(const isr_param* param)
             pos->counter = pos->deadline;
         } else {
             llist_delete(&pos->link);
-            lxfree(pos);
+            cake_release(timer_pile, pos);
         }
     }
 
@@ -211,12 +224,6 @@ timer_update(const isr_param* param)
     }
 }
 
-void
-sched_yield()
-{
-    sched_ticks_counter = sched_ticks;
-}
-
 static void
 temp_intr_routine_rtc_tick(const isr_param* param)
 {