Decoupling Architectural-specific Code (#35)
[lunaix-os.git] / lunaix-os / hal / pci.c
index 3e4a3fefdee13be652758b2d26c966aa68467bdf..af7a256f50b47614298cc213eb8821a83f40059d 100644 (file)
@@ -22,7 +22,7 @@ LOG_MODULE("PCI")
 static DEFINE_LLIST(pci_devices);
 static DECLARE_HASHTABLE(pci_devcache, 8);
 
 static DEFINE_LLIST(pci_devices);
 static DECLARE_HASHTABLE(pci_devcache, 8);
 
-static struct device* pcidev_cat;
+static struct device_cat* pcidev_cat;
 static struct device_def pci_def;
 
 void
 static struct device_def pci_def;
 
 void
@@ -34,29 +34,19 @@ pci_log_device(struct pci_device* pcidev)
     pciaddr_t loc = pcidev->loc;
     struct device_def* binddef = pcidev->binding.def;
 
     pciaddr_t loc = pcidev->loc;
     struct device_def* binddef = pcidev->binding.def;
 
-    if (!binddef) {
-        kprintf("pci.%d:%d:%d, no binding",
-                PCILOC_BUS(loc),
-                PCILOC_DEV(loc),
-                PCILOC_FN(loc));
-        return;
-    }
-
-    kprintf("pci.%d:%d:%d, dev.%xh:%xh.%d, %s",
+    kprintf("pci.%03d:%02d:%02d, class=%p, vendor:dev=%04x:%04x",
             PCILOC_BUS(loc),
             PCILOC_DEV(loc),
             PCILOC_FN(loc),
             PCILOC_BUS(loc),
             PCILOC_DEV(loc),
             PCILOC_FN(loc),
-            binddef->class.fn_grp,
-            binddef->class.device,
-            binddef->class.variant,
-            binddef->name);
+            pcidev->class_info,
+            PCI_DEV_VENDOR(pcidev->device_info),
+            PCI_DEV_DEVID(pcidev->device_info));
 }
 
 static struct pci_device*
 pci_create_device(pciaddr_t loc, ptr_t pci_base, int devinfo)
 {
     pci_reg_t class = pci_read_cspace(pci_base, 0x8);
 }
 
 static struct pci_device*
 pci_create_device(pciaddr_t loc, ptr_t pci_base, int devinfo)
 {
     pci_reg_t class = pci_read_cspace(pci_base, 0x8);
-    struct hbucket* bucket = device_definitions_byif(DEVIF_PCI);
 
     u32_t devid = PCI_DEV_DEVID(devinfo);
     u32_t vendor = PCI_DEV_VENDOR(devinfo);
 
     u32_t devid = PCI_DEV_DEVID(devinfo);
     u32_t vendor = PCI_DEV_VENDOR(devinfo);
@@ -68,59 +58,92 @@ pci_create_device(pciaddr_t loc, ptr_t pci_base, int devinfo)
     device->cspace_base = pci_base;
     device->intr_info = intr;
 
     device->cspace_base = pci_base;
     device->intr_info = intr;
 
-    device_create(&device->dev, pcidev_cat, DEV_IFSYS, NULL);
+    device_create(&device->dev, dev_meta(pcidev_cat), DEV_IFSYS, NULL);
 
     pci_probe_msi_info(device);
     pci_probe_bar_info(device);
 
     llist_append(&pci_devices, &device->dev_chain);
 
     pci_probe_msi_info(device);
     pci_probe_bar_info(device);
 
     llist_append(&pci_devices, &device->dev_chain);
-    device_register(&device->dev, &pci_def.class, "%x", loc);
+    register_device(&device->dev, &pci_def.class, "%x", loc);
     pci_def.class.variant++;
 
     pci_def.class.variant++;
 
-    // find a suitable binding
+    return device;
+}
+
+int
+pci_bind_definition(struct pci_device_def* pcidev_def, int* more)
+{
+    u32_t class = pcidev_def->dev_class;
+    u32_t devid_mask = pcidev_def->ident_mask;
+    u32_t devid = pcidev_def->dev_ident & devid_mask;
+
+    if (!pcidev_def->devdef.bind) {
+        ERROR("pcidev %xh:%xh.%d is unbindable",
+              pcidev_def->devdef.class.fn_grp,
+              pcidev_def->devdef.class.device,
+              pcidev_def->devdef.class.variant);
+        return EINVAL;
+    }
+
+    *more = 0;
+
+    int bind_attempted = 0;
+    int errno = 0;
 
 
-    struct pci_device_def *pos, *n;
-    hashtable_bucket_foreach(bucket, pos, n, devdef.hlist_if)
+    struct device_def* devdef;
+    struct pci_device *pos, *n;
+    llist_for_each(pos, n, &pci_devices, dev_chain)
     {
     {
-        if (pos->dev_class != PCI_DEV_CLASS(class)) {
+        if (binded_pcidev(pos)) {
+            continue;
+        }
+
+        if (class != PCI_DEV_CLASS(pos->class_info)) {
             continue;
         }
 
             continue;
         }
 
-        u32_t idm = pos->ident_mask;
-        int result = (pos->dev_ident & idm) == (devinfo & idm);
+        int matched = (pos->device_info & devid_mask) == devid;
 
 
-        if (result) {
-            goto found;
+        if (!matched) {
+            continue;
         }
         }
-    }
 
 
-    goto done;
+        if (bind_attempted) {
+            *more = 1;
+            break;
+        }
 
 
-found:
-    if (!pos->devdef.bind) {
-        kprintf(KERROR "pci_loc:%x, (%xh:%xh.%d) unbindable",
-                loc,
-                pos->devdef.class.fn_grp,
-                pos->devdef.class.device,
-                pos->devdef.class.variant);
-        goto done;
-    }
+        bind_attempted = 1;
+        devdef = &pcidev_def->devdef;
+        errno = devdef->bind(devdef, &pos->dev);
 
 
-    int errno = pos->devdef.bind(&pos->devdef, &device->dev);
-    if (errno) {
-        kprintf(KERROR "pci_loc:%x, (%xh:%xh.%d) failed, e=%d",
-                loc,
-                pos->devdef.class.fn_grp,
-                pos->devdef.class.device,
-                pos->devdef.class.variant,
-                errno);
-        goto done;
+        if (errno) {
+            ERROR("pci_loc:%x, bind (%xh:%xh.%d) failed, e=%d",
+                  pos->loc,
+                  devdef->class.fn_grp,
+                  devdef->class.device,
+                  devdef->class.variant,
+                  errno);
+            continue;
+        }
+
+        pos->binding.def = &pcidev_def->devdef;
     }
 
     }
 
-    device->binding.def = &pos->devdef;
+    return errno;
+}
 
 
-done:
-    return device;
+int
+pci_bind_definition_all(struct pci_device_def* pcidef)
+{
+    int more = 0, e = 0;
+    do {
+        if (!(e = pci_bind_definition(pcidef, &more))) {
+            break;
+        }
+    } while (more);
+
+    return e;
 }
 
 void
 }
 
 void
@@ -191,6 +214,42 @@ pci_probe_bar_info(struct pci_device* device)
     }
 }
 
     }
 }
 
+void
+pci_setup_msi(struct pci_device* device, int vector)
+{
+    // PCI LB Spec. (Rev 3) Section 6.8 & 6.8.1
+
+    ptr_t msi_addr = pci_get_msi_base();
+    u32_t msi_data = pci_config_msi_data(vector);
+
+    pci_reg_t reg1 = pci_read_cspace(device->cspace_base, device->msi_loc);
+    pci_reg_t msg_ctl = reg1 >> 16;
+    int offset_cap64 = !!(msg_ctl & MSI_CAP_64BIT) * 4;
+
+    pci_write_cspace(device->cspace_base, 
+                     PCI_MSI_ADDR_LO(device->msi_loc), 
+                     msi_addr);
+    
+    if (offset_cap64) {
+        pci_write_cspace(device->cspace_base, 
+                         PCI_MSI_ADDR_HI(device->msi_loc), 
+                         (u64_t)msi_addr >> 32);
+    }
+
+    pci_write_cspace(device->cspace_base,
+                     PCI_MSI_DATA(device->msi_loc, offset_cap64),
+                     msi_data & 0xffff);
+
+    if ((msg_ctl & MSI_CAP_MASK)) {
+        pci_write_cspace(
+          device->cspace_base, PCI_MSI_MASK(device->msi_loc, offset_cap64), 0);
+    }
+
+    // manipulate the MSI_CTRL to allow device using MSI to request service.
+    reg1 = (reg1 & 0xff8fffff) | 0x10000;
+    pci_write_cspace(device->cspace_base, device->msi_loc, reg1);
+}
+
 void
 pci_probe_msi_info(struct pci_device* device)
 {
 void
 pci_probe_msi_info(struct pci_device* device)
 {
@@ -418,8 +477,8 @@ pci_bind_instance(struct pci_device* pcidev, void* devobj)
 }
 
 static struct device_def pci_def = {
 }
 
 static struct device_def pci_def = {
-    .name = "pci3.0-hba",
+    .name = "Generic PCI",
     .class = DEVCLASS(DEVIF_SOC, DEVFN_BUSIF, DEV_PCI),
     .init = pci_load_devices
 };
     .class = DEVCLASS(DEVIF_SOC, DEVFN_BUSIF, DEV_PCI),
     .init = pci_load_devices
 };
-EXPORT_DEVICE(pci3hba, &pci_def, load_poststage);
+EXPORT_DEVICE(pci3hba, &pci_def, load_sysconf);