aa64: finalise context switch, page fault handler and syscall

[lunaix-os.git] / lunaix-os / arch / aarch64 / includes / asm / tlb.h

diff --git a/lunaix-os/arch/aarch64/includes/asm/tlb.h b/lunaix-os/arch/aarch64/includes/asm/tlb.h
index 11690d39d4f6153fe1f3104ce4b15b6ea7150c37..6b26a70a7cb59784ea8e8cc19f473936e7980505 100644 (file)
--- a/lunaix-os/arch/aarch64/includes/asm/tlb.h
+++ b/lunaix-os/arch/aarch64/includes/asm/tlb.h
@@ -7,17 +7,17 @@
 #include <asm/aa64_sysinst.h>
 
 #define pack_va(asid, ttl, va)                \
-        (((asid & 0xffff) << 48)            | \
-         ((ttl  & 0b1111) << 44)            | \
-         (pfn(va) & ((1 << 44) - 1)))
+        (((asid & 0xffffUL) << 48)            | \
+         ((ttl  & 0b1111UL) << 44)            | \
+         (pfn(va) & ((1UL << 44) - 1)))
 
 #define pack_rva(asid, ttl, base, n, scale)   \
-        (((asid    & 0xffff) << 48)         | \
-         ((_MMU_TG & 0b11) << 46)           | \
-         ((n       & 0x1f) << 39)           | \
-         ((scale   & 0b11) << 37)           | \
-         ((ttl     & 0b1111) << 44)         | \
-         (pfn(base)& ((1 << 37) - 1)))
+        (((asid    & 0xffffUL) << 48)         | \
+         ((_MMU_TG & 0b11UL) << 46)           | \
+         ((n       & 0x1fUL) << 39)           | \
+         ((scale   & 0b11UL) << 37)           | \
+         ((ttl     & 0b1111UL) << 44)         | \
+         (pfn(base)& ((1UL << 37) - 1)))
 
 /**
  * @brief Invalidate an entry of all address space
@@ -28,6 +28,7 @@ static inline void must_inline
 __tlb_invalidate(ptr_t va) 
 {
     sys_a1(tlbi_vaae1, pack_va(0, 0, va));
+    data_barrier;
 }
 
 /**
@@ -40,6 +41,7 @@ static inline void must_inline
 __tlb_flush_asid(unsigned int asid, ptr_t va) 
 {
     sys_a1(tlbi_vae1, pack_va(asid, 0, va));
+    data_barrier;
 }
 
 /**
@@ -62,6 +64,7 @@ static inline void must_inline
 __tlb_flush_all() 
 {
     sys_a0(tlbi_alle1);
+    data_barrier;
 }
 
 /**
@@ -73,6 +76,7 @@ static inline void must_inline
 __tlb_flush_asid_all(unsigned int asid) 
 {
     sys_a1(tlbi_aside1, pack_va(asid, 0, 0));
+    data_barrier;
 }
 
 
@@ -93,6 +97,7 @@ tlb_flush_range(ptr_t addr, unsigned int npages)
     }
 #else
     sys_a1(tlbi_rvaae1, pack_rva(0, 0, addr, npages, 0));
+    data_barrier;
 #endif
 }
 
@@ -114,6 +119,7 @@ tlb_flush_asid_range(unsigned int asid, ptr_t addr, unsigned int npages)
     }
 #else
     sys_a1(tlbi_rvae1, pack_rva(asid, 0, addr, npages, 0));
+    data_barrier;
 #endif
 }