Merge branch 'master' into isa/arm64

[lunaix-os.git] / lunaix-os / arch / aarch64 / includes / asm / aa64_msrs.h

diff --git a/lunaix-os/arch/aarch64/includes/asm/aa64_msrs.h b/lunaix-os/arch/aarch64/includes/asm/aa64_msrs.h
index cd8978d71f1fe45f9453936633df0f4384761220..f1da5f2fa3ac650e7bc971a5208f816884e596bb 100644 (file)
--- a/lunaix-os/arch/aarch64/includes/asm/aa64_msrs.h
+++ b/lunaix-os/arch/aarch64/includes/asm/aa64_msrs.h
@@ -1,10 +1,7 @@
 #ifndef __LUNAIX_AA64_MSRS_H
 #define __LUNAIX_AA64_MSRS_H
 
 #ifndef __LUNAIX_AA64_MSRS_H
 #define __LUNAIX_AA64_MSRS_H
 

-#include <lunaix/compiler.h>
-
-#define __sr_encode(op0, op1, crn, crm, op2)    \
-            s##op0##_##op1##_c##crn##_c##crm##_##op2
+#include "aa64_asm.h"

 
 #define SCTLR_EL1       __sr_encode(3, 0,  1,  0, 0)
 #define TCR_EL1         __sr_encode(3, 0,  2,  0, 2)
 
 #define SCTLR_EL1       __sr_encode(3, 0,  1,  0, 0)
 #define TCR_EL1         __sr_encode(3, 0,  2,  0, 2)


@@ -20,6 +17,7 @@
 #define SP_EL0          __sr_encode(3, 0,  4,  1, 0)
 #define SP_EL1          __sr_encode(3, 4,  4,  1, 0)
 
 #define SP_EL0          __sr_encode(3, 0,  4,  1, 0)
 #define SP_EL1          __sr_encode(3, 4,  4,  1, 0)
 

+#ifndef __ASM__

 #define read_sysreg(reg)                                    \
         ({  unsigned long _x;                               \
             asm ("mrs %0, " stringify(reg):"=r"(_x));       \
 #define read_sysreg(reg)                                    \
         ({  unsigned long _x;                               \
             asm ("mrs %0, " stringify(reg):"=r"(_x));       \


@@ -43,35 +41,14 @@
 #define SCTRL_A             (1UL << 1)
 #define SCTRL_M             (1UL << 0)
 
 #define SCTRL_A             (1UL << 1)
 #define SCTRL_M             (1UL << 0)
 

-#define TCR_DS              (1UL << 59)
-#define TCR_E0PD1           (1UL << 56)
-#define TCR_E0PD0           (1UL << 55)
-#define TCR_TBID1           (1UL << 52)
-#define TCR_TBID0           (1UL << 51)
-#define TCR_HPD1            (1UL << 42)
-#define TCR_HPD0            (1UL << 41)
-#define TCR_HD              (1UL << 40)
-#define TCR_HA              (1UL << 39)
-#define TCR_TBI1            (1UL << 38)
-#define TCR_TBI0            (1UL << 37)
-#define TCR_AS              (1UL << 36)
-
-#define TCR_G4K             (0b01)
-#define TCR_G16K            (0b10)
-#define TCR_G64K            (0b11)
-
-#define TCR_SHNS            (0b01)
-#define TCR_SHOS            (0b10)
-#define TCR_SHIS            (0b11)
-
-#define TCR_TG1(g)          (((g) & 0b11) << 30)
-#define TCR_TG0(g)          (((g) & 0b11) << 14)
-
-#define TCR_T1SZ(sz)        (((sz) & 0b111111) << 16)
-#define TCR_T0SZ(sz)        (((sz) & 0b111111))
-
-#define TCR_EPD1            (1UL << 23)
-#define TCR_EPD0            (1UL << 7)
-#define TCR_A1              (1UL << 22)
+#define sysreg_flagging(reg, set, unset)                    \
+        ({                                                  \
+            unsigned long _x;                               \
+            _x = read_sysreg(reg);                          \
+            _x = (_x & ~(unset)) | (set);                   \
+            set_sysreg(reg, _x);                            \
+            _x;                                             \
+        })

 
 

+#endif

 #endif /* __LUNAIX_AA64_MSRS_H */
 #endif /* __LUNAIX_AA64_MSRS_H */