* @copyright Copyright (c) 2022
*
*/
-#include <hal/acpi/acpi.h>
-#include <hal/apic.h>
#include <hal/pci.h>
+#include <sys/pci_hba.h>
+
+#include <klibc/string.h>
#include <lunaix/fs/twifs.h>
#include <lunaix/mm/valloc.h>
#include <lunaix/spike.h>
LOG_MODULE("PCI")
-static struct llist_header pci_devices;
+static DEFINE_LLIST(pci_devices);
+static DECLARE_HASHTABLE(pci_devcache, 8);
+
+static struct device_cat* pcidev_cat;
+static struct device_def pci_def;
void
pci_probe_msi_info(struct pci_device* device);
+static inline void
+pci_log_device(struct pci_device* pcidev)
+{
+ pciaddr_t loc = pcidev->loc;
+ struct device_def* binddef = pcidev->binding.def;
+
+ kprintf("pci.%03d:%02d:%02d, class=%p, vendor:dev=%04x:%04x",
+ PCILOC_BUS(loc),
+ PCILOC_DEV(loc),
+ PCILOC_FN(loc),
+ pcidev->class_info,
+ PCI_DEV_VENDOR(pcidev->device_info),
+ PCI_DEV_DEVID(pcidev->device_info));
+}
+
+static struct pci_device*
+pci_create_device(pciaddr_t loc, ptr_t pci_base, int devinfo)
+{
+ pci_reg_t class = pci_read_cspace(pci_base, 0x8);
+
+ u32_t devid = PCI_DEV_DEVID(devinfo);
+ u32_t vendor = PCI_DEV_VENDOR(devinfo);
+ pci_reg_t intr = pci_read_cspace(pci_base, 0x3c);
+
+ struct pci_device* device = vzalloc(sizeof(struct pci_device));
+ device->class_info = class;
+ device->device_info = devinfo;
+ device->cspace_base = pci_base;
+ device->intr_info = intr;
+
+ device_create(&device->dev, dev_meta(pcidev_cat), DEV_IFSYS, NULL);
+
+ pci_probe_msi_info(device);
+ pci_probe_bar_info(device);
+
+ llist_append(&pci_devices, &device->dev_chain);
+ register_device(&device->dev, &pci_def.class, "%x", loc);
+ pci_def.class.variant++;
+
+ return device;
+}
+
+int
+pci_bind_definition(struct pci_device_def* pcidev_def, int* more)
+{
+ u32_t class = pcidev_def->dev_class;
+ u32_t devid_mask = pcidev_def->ident_mask;
+ u32_t devid = pcidev_def->dev_ident & devid_mask;
+
+ if (!pcidev_def->devdef.bind) {
+ ERROR("pcidev %xh:%xh.%d is unbindable",
+ pcidev_def->devdef.class.fn_grp,
+ pcidev_def->devdef.class.device,
+ pcidev_def->devdef.class.variant);
+ return EINVAL;
+ }
+
+ *more = 0;
+
+ int bind_attempted = 0;
+ int errno = 0;
+
+ struct device_def* devdef;
+ struct pci_device *pos, *n;
+ llist_for_each(pos, n, &pci_devices, dev_chain)
+ {
+ if (binded_pcidev(pos)) {
+ continue;
+ }
+
+ if (class != PCI_DEV_CLASS(pos->class_info)) {
+ continue;
+ }
+
+ int matched = (pos->device_info & devid_mask) == devid;
+
+ if (!matched) {
+ continue;
+ }
+
+ if (bind_attempted) {
+ *more = 1;
+ break;
+ }
+
+ bind_attempted = 1;
+ devdef = &pcidev_def->devdef;
+ errno = devdef->bind(devdef, &pos->dev);
+
+ if (errno) {
+ ERROR("pci_loc:%x, bind (%xh:%xh.%d) failed, e=%d",
+ pos->loc,
+ devdef->class.fn_grp,
+ devdef->class.device,
+ devdef->class.variant,
+ errno);
+ continue;
+ }
+
+ pos->binding.def = &pcidev_def->devdef;
+ }
+
+ return errno;
+}
+
+int
+pci_bind_definition_all(struct pci_device_def* pcidef)
+{
+ int more = 0, e = 0;
+ do {
+ if (!(e = pci_bind_definition(pcidef, &more))) {
+ break;
+ }
+ } while (more);
+
+ return e;
+}
+
void
-pci_probe_device(int bus, int dev, int funct)
+pci_probe_device(pciaddr_t pci_loc)
{
- uint32_t base = PCI_ADDRESS(bus, dev, funct);
+ u32_t base = PCI_CFGADDR(pci_loc);
pci_reg_t reg1 = pci_read_cspace(base, 0);
// Vendor=0xffff则表示设备不存在
// 防止堆栈溢出
// QEMU的ICH9/Q35实现似乎有点问题，对于多功能设备的每一个功能的header type
// 都将第七位置位。而virtualbox 就没有这个毛病。
- if ((hdr_type & 0x80) && funct == 0) {
+ if ((hdr_type & 0x80) && PCILOC_FN(pci_loc) == 0) {
hdr_type = hdr_type & ~0x80;
// 探测多用途设备（multi-function device）
for (int i = 1; i < 7; i++) {
- pci_probe_device(bus, dev, i);
+ pci_probe_device(pci_loc + i);
}
}
- if (hdr_type != PCI_TDEV) {
- // XXX: 目前忽略所有桥接设备，比如PCI-PCI桥接器，或者是CardBus桥接器
- return;
+ struct pci_device *pos, *n;
+ hashtable_hash_foreach(pci_devcache, pci_loc, pos, n, dev_cache)
+ {
+ if (pos->loc == pci_loc) {
+ pci_log_device(pos);
+ return;
+ }
}
- pci_reg_t intr = pci_read_cspace(base, 0x3c);
- pci_reg_t class = pci_read_cspace(base, 0x8);
-
- struct pci_device* device = vzalloc(sizeof(struct pci_device));
- *device = (struct pci_device){ .cspace_base = base,
- .class_info = class,
- .device_info = reg1,
- .intr_info = intr };
-
- pci_probe_msi_info(device);
- pci_probe_bar_info(device);
-
- llist_append(&pci_devices, &device->dev_chain);
+ struct pci_device* pcidev = pci_create_device(pci_loc, base, reg1);
+ if (pcidev) {
+ pcidev->loc = pci_loc;
+ hashtable_hash_in(pci_devcache, &pcidev->dev_cache, pci_loc);
+ pci_log_device(pcidev);
+ }
}
void
-pci_probe()
+pci_scan()
{
- // 暴力扫描所有PCI设备
- // XXX: 尽管最多会有256条PCI总线，但就目前而言，只考虑bus #0就足够了
- for (int bus = 0; bus < 1; bus++) {
- for (int dev = 0; dev < 32; dev++) {
- pci_probe_device(bus, dev, 0);
- }
+ for (u32_t loc = 0; loc < (pciaddr_t)-1; loc += 8) {
+ pci_probe_device((pciaddr_t)loc);
}
}
void
pci_probe_bar_info(struct pci_device* device)
{
- uint32_t bar;
+ u32_t bar;
struct pci_base_addr* ba;
for (size_t i = 0; i < 6; i++) {
ba = &device->bar[i];
}
pci_reg_t cap_ptr = pci_read_cspace(device->cspace_base, 0x34) & 0xff;
- uint32_t cap_hdr;
+ u32_t cap_hdr;
while (cap_ptr) {
cap_hdr = pci_read_cspace(device->cspace_base, cap_ptr);
}
}
-void
+size_t
+pci_bar_sizing(struct pci_device* dev, u32_t* bar_out, u32_t bar_num)
+{
+ pci_reg_t bar = pci_read_cspace(dev->cspace_base, PCI_REG_BAR(bar_num));
+ if (!bar) {
+ *bar_out = 0;
+ return 0;
+ }
+
+ pci_write_cspace(dev->cspace_base, PCI_REG_BAR(bar_num), 0xffffffff);
+ pci_reg_t sized =
+ pci_read_cspace(dev->cspace_base, PCI_REG_BAR(bar_num)) & ~0x1;
+ if (PCI_BAR_MMIO(bar)) {
+ sized = PCI_BAR_ADDR_MM(sized);
+ }
+ *bar_out = bar;
+ pci_write_cspace(dev->cspace_base, PCI_REG_BAR(bar_num), bar);
+ return ~sized + 1;
+}
+
+struct pci_device*
+pci_get_device_by_id(u16_t vendorId, u16_t deviceId)
+{
+ u32_t dev_info = vendorId | (deviceId << 16);
+ struct pci_device *pos, *n;
+ llist_for_each(pos, n, &pci_devices, dev_chain)
+ {
+ if (pos->device_info == dev_info) {
+ return pos;
+ }
+ }
+
+ return NULL;
+}
+
+struct pci_device*
+pci_get_device_by_class(u32_t class)
+{
+ struct pci_device *pos, *n;
+ llist_for_each(pos, n, &pci_devices, dev_chain)
+ {
+ if (PCI_DEV_CLASS(pos->class_info) == class) {
+ return pos;
+ }
+ }
+
+ return NULL;
+}
+
+static void
__pci_read_cspace(struct twimap* map)
{
struct pci_device* pcidev = (struct pci_device*)(map->data);
map->size_acc = 256;
}
-void
+/*---------- TwiFS interface definition ----------*/
+
+static void
__pci_read_revid(struct twimap* map)
{
int class = twimap_data(map, struct pci_device*)->class_info;
twimap_printf(map, "0x%x", PCI_DEV_REV(class));
}
-void
+static void
__pci_read_class(struct twimap* map)
{
int class = twimap_data(map, struct pci_device*)->class_info;
twimap_printf(map, "0x%x", PCI_DEV_CLASS(class));
}
-void
+static void
+__pci_read_devinfo(struct twimap* map)
+{
+ int devinfo = twimap_data(map, struct pci_device*)->device_info;
+ twimap_printf(
+ map, "%x:%x", PCI_DEV_VENDOR(devinfo), PCI_DEV_DEVID(devinfo));
+}
+
+static void
__pci_bar_read(struct twimap* map)
{
struct pci_device* pcidev = twimap_data(map, struct pci_device*);
}
twimap_printf(
- map, "[%d] base=%p, size=%p, ", bar_index, bar->start, bar->size);
+ map, "[%d] base=%.8p, size=%.8p, ", bar_index, bar->start, bar->size);
if ((bar->type & BAR_TYPE_MMIO)) {
twimap_printf(map, "mmio");
if ((bar->type & BAR_TYPE_CACHABLE)) {
- twimap_printf(map, ", cachable");
+ twimap_printf(map, ", prefetchable");
}
} else {
twimap_printf(map, "io");
twimap_printf(map, "\n");
}
-int
+static int
__pci_bar_gonext(struct twimap* map)
{
if (twimap_index(map, int) >= 5) {
return 1;
}
+static void
+__pci_read_binding(struct twimap* map)
+{
+ struct pci_device* pcidev = twimap_data(map, struct pci_device*);
+ struct device_def* devdef = pcidev->binding.def;
+ if (!devdef) {
+ return;
+ }
+
+ twimap_printf(map,
+ "%xh:%xh.%d",
+ devdef->class.fn_grp,
+ devdef->class.device,
+ devdef->class.variant);
+}
+
+static void
+__pci_trigger_bus_rescan(struct twimap* map)
+{
+ pci_scan();
+}
+
void
pci_build_fsmapping()
{
struct twifs_node *pci_class = twifs_dir_node(NULL, "pci"), *pci_dev;
struct pci_device *pos, *n;
struct twimap* map;
+
+ map = twifs_mapping(pci_class, NULL, "rescan");
+ map->read = __pci_trigger_bus_rescan;
+
llist_for_each(pos, n, &pci_devices, dev_chain)
{
- pci_dev = twifs_dir_node(pci_class,
- "%.2d:%.2d:%.2d.%.4x:%.4x",
- PCI_BUS_NUM(pos->cspace_base),
- PCI_SLOT_NUM(pos->cspace_base),
- PCI_FUNCT_NUM(pos->cspace_base),
- PCI_DEV_VENDOR(pos->device_info),
- PCI_DEV_DEVID(pos->device_info));
+ pci_dev = twifs_dir_node(pci_class, "%x", pos->loc);
map = twifs_mapping(pci_dev, pos, "config");
map->read = __pci_read_cspace;
map = twifs_mapping(pci_dev, pos, "class");
map->read = __pci_read_class;
+ map = twifs_mapping(pci_dev, pos, "binding");
+ map->read = __pci_read_binding;
+
map = twifs_mapping(pci_dev, pos, "io_bases");
map->read = __pci_bar_read;
map->go_next = __pci_bar_gonext;
}
}
+EXPORT_TWIFS_PLUGIN(pci_devs, pci_build_fsmapping);
-size_t
-pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num)
-{
- pci_reg_t bar = pci_read_cspace(dev->cspace_base, PCI_REG_BAR(bar_num));
- if (!bar) {
- *bar_out = 0;
- return 0;
- }
+/*---------- PCI 3.0 HBA device definition ----------*/
- pci_write_cspace(dev->cspace_base, PCI_REG_BAR(bar_num), 0xffffffff);
- pci_reg_t sized =
- pci_read_cspace(dev->cspace_base, PCI_REG_BAR(bar_num)) & ~0x1;
- if (PCI_BAR_MMIO(bar)) {
- sized = PCI_BAR_ADDR_MM(sized);
- }
- *bar_out = bar;
- pci_write_cspace(dev->cspace_base, PCI_REG_BAR(bar_num), bar);
- return ~sized + 1;
-}
-
-void
-pci_setup_msi(struct pci_device* device, int vector)
+static int
+pci_load_devices(struct device_def* def)
{
- // Dest: APIC#0, Physical Destination, No redirection
- uint32_t msi_addr = (__APIC_BASE_PADDR);
+ pcidev_cat = device_addcat(NULL, "pci");
- // Edge trigger, Fixed delivery
- uint32_t msi_data = vector;
+ pci_scan();
- pci_write_cspace(
- device->cspace_base, PCI_MSI_ADDR(device->msi_loc), msi_addr);
-
- pci_reg_t reg1 = pci_read_cspace(device->cspace_base, device->msi_loc);
- pci_reg_t msg_ctl = reg1 >> 16;
-
- int offset = !!(msg_ctl & MSI_CAP_64BIT) * 4;
- pci_write_cspace(device->cspace_base,
- PCI_MSI_DATA(device->msi_loc, offset),
- msi_data & 0xffff);
-
- if ((msg_ctl & MSI_CAP_MASK)) {
- pci_write_cspace(
- device->cspace_base, PCI_MSI_MASK(device->msi_loc, offset), 0);
- }
-
- // manipulate the MSI_CTRL to allow device using MSI to request service.
- reg1 = (reg1 & 0xff8fffff) | 0x10000;
- pci_write_cspace(device->cspace_base, device->msi_loc, reg1);
-}
-
-struct pci_device*
-pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId)
-{
- uint32_t dev_info = vendorId | (deviceId << 16);
- struct pci_device *pos, *n;
- llist_for_each(pos, n, &pci_devices, dev_chain)
- {
- if (pos->device_info == dev_info) {
- return pos;
- }
- }
-
- return NULL;
-}
-
-struct pci_device*
-pci_get_device_by_class(uint32_t class)
-{
- struct pci_device *pos, *n;
- llist_for_each(pos, n, &pci_devices, dev_chain)
- {
- if (PCI_DEV_CLASS(pos->class_info) == class) {
- return pos;
- }
- }
-
- return NULL;
+ return 0;
}
void
-pci_init()
+pci_bind_instance(struct pci_device* pcidev, void* devobj)
{
- llist_init_head(&pci_devices);
- acpi_context* acpi = acpi_get_context();
- assert_msg(acpi, "ACPI not initialized.");
- if (acpi->mcfg.alloc_num) {
- // PCIe Enhanced Configuration Mechanism is supported.
- // TODO: support PCIe addressing mechanism
- }
- // Otherwise, fallback to use legacy PCI 3.0 method.
- pci_probe();
+ pcidev->dev.underlay = devobj;
+ pcidev->binding.dev = devobj;
+}
- pci_build_fsmapping();
-}
\ No newline at end of file
+static struct device_def pci_def = {
+ .name = "Generic PCI",
+ .class = DEVCLASS(DEVIF_SOC, DEVFN_BUSIF, DEV_PCI),
+ .init = pci_load_devices
+};
+EXPORT_DEVICE(pci3hba, &pci_def, load_sysconf);
git://scm.lunaixsky.com / lunaix-os.git / blobdiff