feat: device subsystem rework

[lunaix-os.git] / lunaix-os / includes / hal / pci.h

diff --git a/lunaix-os/includes/hal/pci.h b/lunaix-os/includes/hal/pci.h
index 95d5fb80f0c17d12b1c1028c1977d1a0dbdd4480..186c6773aadfadafc16875319817e4b4232fc601 100644 (file)
--- a/lunaix-os/includes/hal/pci.h
+++ b/lunaix-os/includes/hal/pci.h
@@ -1,11 +1,10 @@
 #ifndef __LUNAIX_PCI_H
 #define __LUNAIX_PCI_H
 
-#include <hal/io.h>
+#include <lunaix/device.h>
+#include <lunaix/ds/ldga.h>
 #include <lunaix/ds/llist.h>
-
-#define PCI_CONFIG_ADDR 0xcf8
-#define PCI_CONFIG_DATA 0xcfc
+#include <lunaix/types.h>
 
 #define PCI_TDEV 0x0
 #define PCI_TPCIBRIDGE 0x1
@@ -18,7 +17,7 @@
 #define PCI_REG_BAR(num) (0x10 + (num - 1) * 4)
 
 #define PCI_DEV_VENDOR(x) ((x)&0xffff)
-#define PCI_DEV_DEVID(x) ((x) >> 16)
+#define PCI_DEV_DEVID(x) (((x)&0xffff0000) >> 16)
 #define PCI_INTR_IRQ(x) ((x)&0xff)
 #define PCI_INTR_PIN(x) (((x)&0xff00) >> 8)
 #define PCI_DEV_CLASS(x) ((x) >> 8)
@@ -51,6 +50,8 @@
     (((bus)&0xff) << 16) | (((dev)&0xff) << 11) | (((funct)&0xff) << 8) |      \
       0x80000000
 
+#define PCI_ID_ANY (-1)
+
 typedef unsigned int pci_reg_t;
 
 // PCI device header format
@@ -58,49 +59,36 @@ typedef unsigned int pci_reg_t;
 
 #define BAR_TYPE_MMIO 0x1
 #define BAR_TYPE_CACHABLE 0x2
+#define PCI_DRV_NAME_LEN 32
 
 struct pci_base_addr
 {
-    uint32_t start;
-    uint32_t size;
-    uint32_t type;
+    u32_t start;
+    u32_t size;
+    u32_t type;
 };
 
 struct pci_device
 {
+    struct device dev;
     struct llist_header dev_chain;
-    uint32_t device_info;
-    uint32_t class_info;
-    uint32_t cspace_base;
-    uint32_t msi_loc;
-    uint16_t intr_info;
+    u32_t device_info;
+    u32_t class_info;
+    u32_t cspace_base;
+    u32_t msi_loc;
+    u16_t intr_info;
     struct pci_base_addr bar[6];
 };
 
-// PCI Configuration Space (C-Space) r/w:
-//      Refer to "PCI Local Bus Specification, Rev.3, Section 3.2.2.3.2"
+typedef void* (*pci_drv_init)(struct pci_device*);
 
-static inline pci_reg_t
-pci_read_cspace(uint32_t base, int offset)
+struct pci_device_def
 {
-    io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
-    return io_inl(PCI_CONFIG_DATA);
-}
-
-static inline void
-pci_write_cspace(uint32_t base, int offset, pci_reg_t data)
-{
-    io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
-    io_outl(PCI_CONFIG_DATA, data);
-}
-
-/**
- * @brief 初始化PCI。这主要是通过扫描PCI总线进行拓扑重建。注意，该
- * 初始化不包括针对每个设备的初始化，因为那是设备驱动的事情。
- *
- */
-void
-pci_init();
+    u32_t dev_class;
+    u32_t dev_vendor;
+    u32_t dev_id;
+    struct device_def devdef;
+};
 
 /**
  * @brief 根据类型代码（Class Code）去在拓扑中寻找一个设备
@@ -108,7 +96,7 @@ pci_init();
  *
  * @return struct pci_device*
  */
-struct pci_device* pci_get_device_by_class(uint32_t class);
+struct pci_device* pci_get_device_by_class(u32_t class);
 
 /**
  * @brief 根据设备商ID和设备ID，在拓扑中寻找一个设备
@@ -118,7 +106,7 @@ struct pci_device* pci_get_device_by_class(uint32_t class);
  * @return struct pci_device*
  */
 struct pci_device*
-pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId);
+pci_get_device_by_id(u16_t vendorId, u16_t deviceId);
 
 /**
  * @brief 初始化PCI设备的基地址寄存器。返回由该基地址代表的，
@@ -131,17 +119,22 @@ pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId);
  * @return size_t
  */
 size_t
-pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num);
+pci_bar_sizing(struct pci_device* dev, u32_t* bar_out, u32_t bar_num);
+
+void
+pci_add_driver(const char* name,
+               u32_t class,
+               u32_t vendor,
+               u32_t devid,
+               pci_drv_init init);
+
+int
+pci_bind_driver(struct pci_device* pci_dev);
+
+void
+pci_probe_bar_info(struct pci_device* device);
 
-/**
- * @brief 配置并启用设备MSI支持。
- * 参阅：PCI LB Spec. (Rev 3) Section 6.8 & 6.8.1
- * 以及：Intel Manual, Vol 3, Section 10.11
- *
- * @param device PCI device
- * @param vector interrupt vector.
- */
 void
-pci_setup_msi(struct pci_device* device, int vector);
+pci_probe_msi_info(struct pci_device* device);
 
 #endif /* __LUNAIX_PCI_H */