update readme

[lunaix-os.git] / lunaix-os / hal / pci.c

diff --git a/lunaix-os/hal/pci.c b/lunaix-os/hal/pci.c
index 32299cdf8d2fa24d4302b9110585ac1b2f68a8e3..8c397b031b85f739b2331aeb2b512cb3931756b9 100644 (file)
--- a/lunaix-os/hal/pci.c
+++ b/lunaix-os/hal/pci.c
@@ -1,3 +1,13 @@
+/**
+ * @file pci.c
+ * @author Lunaixsky (zelong56@gmail.com)
+ * @brief A software implementation of PCI Local Bus Specification Revision 3.0
+ * @version 0.1
+ * @date 2022-06-28
+ *
+ * @copyright Copyright (c) 2022
+ *
+ */
 #include <hal/acpi/acpi.h>
 #include <hal/apic.h>
 #include <hal/pci.h>
@@ -156,6 +166,7 @@ pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num)
         sized = PCI_BAR_ADDR_MM(sized);
     }
     *bar_out = bar;
+    pci_write_cspace(dev->cspace_base, PCI_REG_BAR(bar_num), bar);
     return ~sized + 1;
 }
 
@@ -163,20 +174,29 @@ void
 pci_setup_msi(struct pci_device* device, int vector)
 {
     // Dest: APIC#0, Physical Destination, No redirection
-    uint32_t msi_addr = (__APIC_BASE_PADDR | 0x8);
+    uint32_t msi_addr = (__APIC_BASE_PADDR);
 
     // Edge trigger, Fixed delivery
     uint32_t msi_data = vector;
 
     pci_write_cspace(
       device->cspace_base, PCI_MSI_ADDR(device->msi_loc), msi_addr);
-    pci_write_cspace(
-      device->cspace_base, PCI_MSI_DATA(device->msi_loc), msi_data & 0xffff);
 
     pci_reg_t reg1 = pci_read_cspace(device->cspace_base, device->msi_loc);
+    pci_reg_t msg_ctl = reg1 >> 16;
+
+    int offset = !!(msg_ctl & MSI_CAP_64BIT) * 4;
+    pci_write_cspace(device->cspace_base,
+                     PCI_MSI_DATA(device->msi_loc, offset),
+                     msi_data & 0xffff);
+
+    if ((msg_ctl & MSI_CAP_MASK)) {
+        pci_write_cspace(
+          device->cspace_base, PCI_MSI_MASK(device->msi_loc, offset), 0);
+    }
 
     // manipulate the MSI_CTRL to allow device using MSI to request service.
-    reg1 = ((((reg1 >> 16) & ~0x70) | 0x1) << 16) | (reg1 & 0xffff);
+    reg1 = ((((reg1 >> 16) & ~0x70) | MSI_CAP_ENABLE) << 16) | (reg1 & 0xffff);
     pci_write_cspace(device->cspace_base, device->msi_loc, reg1);
 }