PCI 16x50 UART Controller, O2 Enablement (#39)

[lunaix-os.git] / lunaix-os / includes / hal / pci.h

diff --git a/lunaix-os/includes/hal/pci.h b/lunaix-os/includes/hal/pci.h
index 8c18997bc4fc14f0b96f278e70968c17557d5241..d457a1ed276da5d78398e9869ba1f05a1492e9e9 100644 (file)
--- a/lunaix-os/includes/hal/pci.h
+++ b/lunaix-os/includes/hal/pci.h
@@ -6,8 +6,8 @@
 #include <lunaix/ds/llist.h>
 #include <lunaix/types.h>
 
-#define EXPORT_PCI_DEVICE(id, pci_devdef)                                      \
-    EXPORT_DEVICE(id, &(pci_devdef)->devdef, load_pci_probe)
+#define EXPORT_PCI_DEVICE(id, pci_devdef, stage)                               \
+    EXPORT_DEVICE(id, &(pci_devdef)->devdef, stage)
 
 #define PCI_MATCH_EXACT -1
 #define PCI_MATCH_ANY 0
@@ -38,8 +38,10 @@
 #define PCI_BAR_TYPE(x) ((x) & 0x6)
 #define PCI_BAR_ADDR_MM(x) ((x) & ~0xf)
 #define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)
+#define PCI_BAR_COUNT 6
 
-#define PCI_MSI_ADDR(msi_base) ((msi_base) + 4)
+#define PCI_MSI_ADDR_LO(msi_base) ((msi_base) + 4)
+#define PCI_MSI_ADDR_HI(msi_base) ((msi_base) + 8)
 #define PCI_MSI_DATA(msi_base, offset) ((msi_base) + 8 + offset)
 #define PCI_MSI_MASK(msi_base, offset) ((msi_base) + 0xc + offset)
 
@@ -53,13 +55,18 @@
 #define PCI_RCMD_MM_ACCESS (1 << 1)
 #define PCI_RCMD_IO_ACCESS 1
 
-#define PCI_ADDRESS(bus, dev, funct)                                           \
-    (((bus) & 0xff) << 16) | (((dev) & 0xff) << 11) |                          \
-      (((funct) & 0xff) << 8) | 0x80000000
+#define PCI_CFGADDR(pciloc) ((u32_t)(pciloc) << 8) | 0x80000000UL
+
+#define PCILOC(bus, dev, funct)                                                \
+    (((bus) & 0xff) << 8) | (((dev) & 0x1f) << 3) | ((funct) & 0x7)
+#define PCILOC_BUS(loc) (((loc) >> 8) & 0xff)
+#define PCILOC_DEV(loc) (((loc) >> 3) & 0x1f)
+#define PCILOC_FN(loc) ((loc) & 0x7)
 
 #define PCI_ID_ANY (-1)
 
 typedef unsigned int pci_reg_t;
+typedef u16_t pciaddr_t;
 
 // PCI device header format
 // Ref: "PCI Local Bus Specification, Rev.3, Section 6.1"
@@ -79,15 +86,30 @@ struct pci_device
 {
     struct device dev;
     struct llist_header dev_chain;
+    struct hlist_node dev_cache;
+
+    struct
+    {
+        struct device* dev;
+        struct device_def* def;
+    } binding;
+
+    pciaddr_t loc;
+    u16_t intr_info;
     u32_t device_info;
     u32_t class_info;
     u32_t cspace_base;
     u32_t msi_loc;
-    u16_t intr_info;
     struct pci_base_addr bar[6];
 };
 #define PCI_DEVICE(devbase) (container_of((devbase), struct pci_device, dev))
 
+struct pci_device_list
+{
+    struct llist_header peers;
+    struct pci_device* pcidev;
+};
+
 typedef void* (*pci_drv_init)(struct pci_device*);
 
 #define PCI_DEVIDENT(vendor, id)                                               \
@@ -95,11 +117,14 @@ typedef void* (*pci_drv_init)(struct pci_device*);
 
 struct pci_device_def
 {
-    u32_t dev_class;
-    u32_t dev_ident;
-    u32_t ident_mask;
     struct device_def devdef;
+
+    bool (*test_compatibility)(struct pci_device_def*, struct pci_device*);
 };
+#define pcidev_def(dev_def_ptr)                                                \
+    container_of((dev_def_ptr), struct pci_device_def, devdef)
+
+#define binded_pcidev(pcidev) ((pcidev)->binding.def)
 
 /**
  * @brief 根据类型代码（Class Code）去在拓扑中寻找一个设备
@@ -132,20 +157,117 @@ pci_get_device_by_id(u16_t vendorId, u16_t deviceId);
 size_t
 pci_bar_sizing(struct pci_device* dev, u32_t* bar_out, u32_t bar_num);
 
+/**
+ * @brief Bind an abstract device instance to the pci device
+ *
+ * @param pcidev pci device
+ * @param devobj abstract device instance
+ */
 void
-pci_add_driver(const char* name,
-               u32_t class,
-               u32_t vendor,
-               u32_t devid,
-               pci_drv_init init);
-
-int
-pci_bind_driver(struct pci_device* pci_dev);
+pci_bind_instance(struct pci_device* pcidev, void* devobj);
 
 void
 pci_probe_bar_info(struct pci_device* device);
 
+void
+pci_setup_msi(struct pci_device* device, int vector);
+
 void
 pci_probe_msi_info(struct pci_device* device);
 
+int
+pci_bind_definition(struct pci_device_def* pcidev_def, bool* more);
+
+int
+pci_bind_definition_all(struct pci_device_def* pcidef);
+
+static inline unsigned int
+pci_device_vendor(struct pci_device* pcidev)
+{
+    return PCI_DEV_VENDOR(pcidev->device_info);
+}
+
+static inline unsigned int
+pci_device_devid(struct pci_device* pcidev)
+{
+    return PCI_DEV_DEVID(pcidev->device_info);
+}
+
+static inline unsigned int
+pci_device_class(struct pci_device* pcidev)
+{
+    return PCI_DEV_CLASS(pcidev->class_info);
+}
+
+static inline struct pci_base_addr*
+pci_device_bar(struct pci_device* pcidev, int index)
+{
+    return &pcidev->bar[index];
+}
+
+static inline void
+pci_cmd_set_mmio(pci_reg_t* cmd)
+{
+    *cmd |= PCI_RCMD_MM_ACCESS;
+}
+
+
+static inline void
+pci_cmd_set_pmio(pci_reg_t* cmd)
+{
+    *cmd |= PCI_RCMD_IO_ACCESS;
+}
+
+static inline void
+pci_cmd_set_msi(pci_reg_t* cmd)
+{
+    *cmd |= PCI_RCMD_DISABLE_INTR;
+}
+
+static inline void
+pci_cmd_set_bus_master(pci_reg_t* cmd)
+{
+    *cmd |= PCI_RCMD_BUS_MASTER;
+}
+
+static inline void
+pci_cmd_set_fast_b2b(pci_reg_t* cmd)
+{
+    *cmd |= PCI_RCMD_FAST_B2B;
+}
+
+static inline bool
+pci_bar_mmio_space(struct pci_base_addr* bar)
+{
+    return (bar->type & BAR_TYPE_MMIO);
+}
+
+static inline bool
+pci_capability_msi(struct pci_device* pcidev)
+{
+    return !!pcidev->msi_loc;
+}
+
+static inline int
+pci_intr_irq(struct pci_device* pcidev)
+{
+    return PCI_INTR_IRQ(pcidev->intr_info);
+}
+
+void
+pci_apply_command(struct pci_device* pcidev, pci_reg_t cmd);
+
+pci_reg_t
+pci_read_cspace(ptr_t base, int offset);
+
+void
+pci_write_cspace(ptr_t base, int offset, pci_reg_t data);
+
+u16_t
+pci_config_msi_data(int vector);
+
+ptr_t
+pci_get_msi_base();
+
+
 #endif /* __LUNAIX_PCI_H */