Support to multi-threading and pthread interface (POSIX.1-2008) (#23)

[lunaix-os.git] / lunaix-os / kernel / mm / vmm.c

diff --git a/lunaix-os/kernel/mm/vmm.c b/lunaix-os/kernel/mm/vmm.c
index 5a868d41734ce9b3aba898cd49c5c9b87764a8a0..5e09e9dada4d5e92e4e48c7bb4c2f2c632de02bf 100644 (file)
--- a/lunaix-os/kernel/mm/vmm.c
+++ b/lunaix-os/kernel/mm/vmm.c
@@ -1,10 +1,12 @@
-#include <hal/cpu.h>
 #include <klibc/string.h>
 #include <lunaix/mm/pmm.h>
 #include <lunaix/mm/vmm.h>
 #include <lunaix/spike.h>
 #include <lunaix/syslog.h>
 
+#include <sys/cpu.h>
+#include <sys/mm/mm_defs.h>
+
 LOG_MODULE("VMM")
 
 void
@@ -17,7 +19,7 @@ x86_page_table*
 vmm_init_pd()
 {
     x86_page_table* dir =
-      (x86_page_table*)pmm_alloc_page(KERNEL_PID, PP_FGPERSIST);
+      (x86_page_table*)pmm_alloc_page(PP_FGPERSIST);
     for (size_t i = 0; i < PG_MAX_ENTRIES; i++) {
         dir->entry[i] = PTE_NULL;
     }
@@ -41,9 +43,10 @@ vmm_set_mapping(ptr_t mnt, ptr_t va, ptr_t pa, pt_attr attr, int options)
     // See if attr make sense
     assert(attr <= 128);
 
-    if (!l1pt->entry[l1_inx]) {
+    x86_pte_t* l1pte = &l1pt->entry[l1_inx];
+    if (!*l1pte) {
         x86_page_table* new_l1pt_pa =
-          (x86_page_table*)pmm_alloc_page(KERNEL_PID, PP_FGPERSIST);
+          (x86_page_table*)pmm_alloc_page(PP_FGPERSIST);
 
         // 物理内存已满！
         if (!new_l1pt_pa) {
@@ -51,14 +54,17 @@ vmm_set_mapping(ptr_t mnt, ptr_t va, ptr_t pa, pt_attr attr, int options)
         }
 
         // This must be writable
-        l1pt->entry[l1_inx] =
-          NEW_L1_ENTRY(attr | PG_WRITE | PG_PRESENT, new_l1pt_pa);
+        *l1pte = NEW_L1_ENTRY(attr | PG_WRITE | PG_PRESENT, new_l1pt_pa);
 
         // make sure our new l2 table is visible to CPU
         cpu_flush_page((ptr_t)l2pt);
 
         memset((void*)l2pt, 0, PG_SIZE);
     } else {
+        if ((attr & PG_ALLOW_USER) && !(*l1pte & PG_ALLOW_USER)) {
+            *l1pte |= PG_ALLOW_USER;
+        }
+
         x86_pte_t pte = l2pt->entry[l2_inx];
         if (pte && (options & VMAP_IGNORE)) {
             return 1;
@@ -73,7 +79,12 @@ vmm_set_mapping(ptr_t mnt, ptr_t va, ptr_t pa, pt_attr attr, int options)
         return 1;
     }
 
-    l2pt->entry[l2_inx] = NEW_L2_ENTRY(attr, pa);
+    if (!(options & VMAP_GUARDPAGE)) {
+        l2pt->entry[l2_inx] = NEW_L2_ENTRY(attr, pa);
+    } else {
+        l2pt->entry[l2_inx] = MEMGUARD;
+    }
+    
     return 1;
 }
 
@@ -182,6 +193,8 @@ vmm_v2pat(ptr_t mnt, ptr_t va)
 ptr_t
 vmm_mount_pd(ptr_t mnt, ptr_t pde)
 {
+    assert(pde);
+
     x86_page_table* l1pt = (x86_page_table*)L1_BASE_VADDR;
     l1pt->entry[(mnt >> 22)] = NEW_L1_ENTRY(T_SELF_REF_PERM, pde);
     cpu_flush_page(mnt);
@@ -195,4 +208,24 @@ vmm_unmount_pd(ptr_t mnt)
     l1pt->entry[(mnt >> 22)] = 0;
     cpu_flush_page(mnt);
     return mnt;
+}
+
+ptr_t
+vmm_dup_page(ptr_t pa)
+{
+    ptr_t new_ppg = pmm_alloc_page(0);
+    vmm_set_mapping(VMS_SELF, PG_MOUNT_3, new_ppg, PG_PREM_RW, VMAP_NULL);
+    vmm_set_mapping(VMS_SELF, PG_MOUNT_4, pa, PG_PREM_RW, VMAP_NULL);
+
+    asm volatile("movl %1, %%edi\n"
+                 "movl %2, %%esi\n"
+                 "rep movsl\n" ::"c"(1024),
+                 "r"(PG_MOUNT_3),
+                 "r"(PG_MOUNT_4)
+                 : "memory", "%edi", "%esi");
+
+    vmm_del_mapping(VMS_SELF, PG_MOUNT_3);
+    vmm_del_mapping(VMS_SELF, PG_MOUNT_4);
+
+    return new_ppg;
 }
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