refactor: one more step towards arch-agnostic design

[lunaix-os.git] / lunaix-os / includes / hal / pci.h

diff --git a/lunaix-os/includes/hal/pci.h b/lunaix-os/includes/hal/pci.h
index 639a12c4de271febd0897b3aa3c7b18896268f58..2cc45b2a77348affaae369fdda855ce36d568c6a 100644 (file)
--- a/lunaix-os/includes/hal/pci.h
+++ b/lunaix-os/includes/hal/pci.h
@@ -1,11 +1,9 @@
 #ifndef __LUNAIX_PCI_H
 #define __LUNAIX_PCI_H
 
 #ifndef __LUNAIX_PCI_H
 #define __LUNAIX_PCI_H
 

-#include <hal/io.h>
+#include <lunaix/ds/ldga.h>

 #include <lunaix/ds/llist.h>
 #include <lunaix/ds/llist.h>

-
-#define PCI_CONFIG_ADDR 0xcf8
-#define PCI_CONFIG_DATA 0xcfc
+#include <lunaix/types.h>

 
 #define PCI_TDEV 0x0
 #define PCI_TPCIBRIDGE 0x1
 
 #define PCI_TDEV 0x0
 #define PCI_TPCIBRIDGE 0x1


@@ -34,7 +32,18 @@
 #define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)
 
 #define PCI_MSI_ADDR(msi_base) ((msi_base) + 4)
 #define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)
 
 #define PCI_MSI_ADDR(msi_base) ((msi_base) + 4)

-#define PCI_MSI_DATA(msi_base) ((msi_base) + 8)
+#define PCI_MSI_DATA(msi_base, offset) ((msi_base) + 8 + offset)
+#define PCI_MSI_MASK(msi_base, offset) ((msi_base) + 0xc + offset)
+
+#define MSI_CAP_64BIT 0x80
+#define MSI_CAP_MASK 0x100
+#define MSI_CAP_ENABLE 0x1
+
+#define PCI_RCMD_DISABLE_INTR (1 << 10)
+#define PCI_RCMD_FAST_B2B (1 << 9)
+#define PCI_RCMD_BUS_MASTER (1 << 2)
+#define PCI_RCMD_MM_ACCESS (1 << 1)
+#define PCI_RCMD_IO_ACCESS 1

 
 #define PCI_ADDRESS(bus, dev, funct)                                           \
     (((bus)&0xff) << 16) | (((dev)&0xff) << 11) | (((funct)&0xff) << 8) |      \
 
 #define PCI_ADDRESS(bus, dev, funct)                                           \
     (((bus)&0xff) << 16) | (((dev)&0xff) << 11) | (((funct)&0xff) << 8) |      \


@@ -45,32 +54,53 @@ typedef unsigned int pci_reg_t;
 // PCI device header format
 // Ref: "PCI Local Bus Specification, Rev.3, Section 6.1"
 
 // PCI device header format
 // Ref: "PCI Local Bus Specification, Rev.3, Section 6.1"
 

+#define BAR_TYPE_MMIO 0x1
+#define BAR_TYPE_CACHABLE 0x2
+#define PCI_DRV_NAME_LEN 32
+
+#define EXPORT_PCI_DEVICE(name_, class, vendor_id, dev_id, init_fn)            \
+    static struct pci_driver pcidev_##name_ =                                  \
+      (struct pci_driver){ .name = #name_,                                     \
+                           .create_driver = (init_fn),                         \
+                           .dev_info = ((vendor_id) << 16) | (dev_id),         \
+                           .dev_class = (class) };                             \
+    export_ldga_el(pci_dev_drivers, name_, ptr_t, &pcidev_##name_)
+
+struct pci_driver;
+
+struct pci_base_addr
+{
+    u32_t start;
+    u32_t size;
+    u32_t type;
+};
+

 struct pci_device
 {
     struct llist_header dev_chain;
 struct pci_device
 {
     struct llist_header dev_chain;

-    uint32_t device_info;
-    uint32_t class_info;
-    uint32_t cspace_base;
-    uint32_t msi_loc;
-    uint16_t intr_info;
+    u32_t device_info;
+    u32_t class_info;
+    u32_t cspace_base;
+    u32_t msi_loc;
+    u16_t intr_info;
+    struct
+    {
+        struct pci_driver* type;
+        void* instance;
+    } driver;
+    struct pci_base_addr bar[6];

 };
 
 };
 

-// PCI Configuration Space (C-Space) r/w:
-//      Refer to "PCI Local Bus Specification, Rev.3, Section 3.2.2.3.2"
-
-inline pci_reg_t
-pci_read_cspace(uint32_t base, int offset)
-{
-    io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
-    return io_inl(PCI_CONFIG_DATA);
-}
+typedef void* (*pci_drv_init)(struct pci_device*);

 
 

-inline void
-pci_write_cspace(uint32_t base, int offset, pci_reg_t data)
+struct pci_driver

 {
 {

-    io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
-    io_outl(PCI_CONFIG_DATA, data);
-}
+    struct llist_header drivers;
+    u32_t dev_info;
+    u32_t dev_class;
+    pci_drv_init create_driver;
+    char name[PCI_DRV_NAME_LEN];
+};

 
 /**
  * @brief 初始化PCI。这主要是通过扫描PCI总线进行拓扑重建。注意，该
 
 /**
  * @brief 初始化PCI。这主要是通过扫描PCI总线进行拓扑重建。注意，该


@@ -78,10 +108,7 @@ pci_write_cspace(uint32_t base, int offset, pci_reg_t data)
  *
  */
 void
  *
  */
 void

-pci_init();
-
-void
-pci_print_device();
+pci_load_devices();

 
 /**
  * @brief 根据类型代码（Class Code）去在拓扑中寻找一个设备
 
 /**
  * @brief 根据类型代码（Class Code）去在拓扑中寻找一个设备


@@ -89,7 +116,7 @@ pci_print_device();
  *
  * @return struct pci_device*
  */
  *
  * @return struct pci_device*
  */

-struct pci_device* pci_get_device_by_class(uint32_t class);
+struct pci_device* pci_get_device_by_class(u32_t class);

 
 /**
  * @brief 根据设备商ID和设备ID，在拓扑中寻找一个设备
 
 /**
  * @brief 根据设备商ID和设备ID，在拓扑中寻找一个设备


@@ -99,7 +126,7 @@ struct pci_device* pci_get_device_by_class(uint32_t class);
  * @return struct pci_device*
  */
 struct pci_device*
  * @return struct pci_device*
  */
 struct pci_device*

-pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId);
+pci_get_device_by_id(u16_t vendorId, u16_t deviceId);

 
 /**
  * @brief 初始化PCI设备的基地址寄存器。返回由该基地址代表的，
 
 /**
  * @brief 初始化PCI设备的基地址寄存器。返回由该基地址代表的，


@@ -112,17 +139,22 @@ pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId);
  * @return size_t
  */
 size_t
  * @return size_t
  */
 size_t

-pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num);
+pci_bar_sizing(struct pci_device* dev, u32_t* bar_out, u32_t bar_num);
+
+void
+pci_add_driver(const char* name,
+               u32_t class,
+               u32_t vendor,
+               u32_t devid,
+               pci_drv_init init);
+
+int
+pci_bind_driver(struct pci_device* pci_dev);
+
+void
+pci_probe_bar_info(struct pci_device* device);

 
 

-/**
- * @brief 配置并启用设备MSI支持。
- * 参阅：PCI LB Spec. (Rev 3) Section 6.8 & 6.8.1
- * 以及：Intel Manual, Vol 3, Section 10.11
- *
- * @param device PCI device
- * @param vector interrupt vector.
- */

 void
 void

-pci_setup_msi(struct pci_device* device, int vector);
+pci_probe_msi_info(struct pci_device* device);

 
 #endif /* __LUNAIX_PCI_H */
 
 #endif /* __LUNAIX_PCI_H */