feat: disk read/write support for both ATA and ATAPI device

[lunaix-os.git] / lunaix-os / hal / pci.c

diff --git a/lunaix-os/hal/pci.c b/lunaix-os/hal/pci.c
index dd4e95b88b0eb156c03f5270471564eb0b3cb4fb..c3771d571e2a10885521d5ecb9922acda7b3efa4 100644 (file)
--- a/lunaix-os/hal/pci.c
+++ b/lunaix-os/hal/pci.c
@@ -1,6 +1,18 @@
+/**
+ * @file pci.c
+ * @author Lunaixsky (zelong56@gmail.com)
+ * @brief A software implementation of PCI Local Bus Specification Revision 3.0
+ * @version 0.1
+ * @date 2022-06-28
+ *
+ * @copyright Copyright (c) 2022
+ *
+ */
+#include <hal/acpi/acpi.h>

 #include <hal/apic.h>
 #include <hal/pci.h>
 #include <lunaix/mm/kalloc.h>
 #include <hal/apic.h>
 #include <hal/pci.h>
 #include <lunaix/mm/kalloc.h>

+#include <lunaix/spike.h>

 #include <lunaix/syslog.h>
 
 LOG_MODULE("PCI")
 #include <lunaix/syslog.h>
 
 LOG_MODULE("PCI")


@@ -24,7 +36,10 @@ pci_probe_device(int bus, int dev, int funct)
     pci_reg_t hdr_type = pci_read_cspace(base, 0xc);
     hdr_type = (hdr_type >> 16) & 0xff;
 
     pci_reg_t hdr_type = pci_read_cspace(base, 0xc);
     hdr_type = (hdr_type >> 16) & 0xff;
 

-    if ((hdr_type & 0x80)) {
+    // 防止堆栈溢出
+    // QEMU的ICH9/Q35实现似乎有点问题，对于多功能设备的每一个功能的header type
+    //  都将第七位置位。而virtualbox 就没有这个毛病。
+    if ((hdr_type & 0x80) && funct == 0) {

         hdr_type = hdr_type & ~0x80;
         // 探测多用途设备（multi-function device）
         for (int i = 1; i < 7; i++) {
         hdr_type = hdr_type & ~0x80;
         // 探测多用途设备（multi-function device）
         for (int i = 1; i < 7; i++) {


@@ -66,6 +81,9 @@ pci_probe()
 void
 pci_probe_msi_info(struct pci_device* device)
 {
 void
 pci_probe_msi_info(struct pci_device* device)
 {

+    // Note that Virtualbox have to use ICH9 chipset for MSI support.
+    // Qemu seems ok with default PIIX3, Bochs is pending to test...
+    //    See https://www.virtualbox.org/manual/ch03.html (section 3.5.1)

     pci_reg_t status =
       pci_read_cspace(device->cspace_base, PCI_REG_STATUS_CMD) >> 16;
 
     pci_reg_t status =
       pci_read_cspace(device->cspace_base, PCI_REG_STATUS_CMD) >> 16;
 


@@ -148,6 +166,7 @@ pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num)
         sized = PCI_BAR_ADDR_MM(sized);
     }
     *bar_out = bar;
         sized = PCI_BAR_ADDR_MM(sized);
     }
     *bar_out = bar;

+    pci_write_cspace(dev->cspace_base, PCI_REG_BAR(bar_num), bar);

     return ~sized + 1;
 }
 
     return ~sized + 1;
 }
 


@@ -205,5 +224,12 @@ void
 pci_init()
 {
     llist_init_head(&pci_devices);
 pci_init()
 {
     llist_init_head(&pci_devices);

+    acpi_context* acpi = acpi_get_context();
+    assert_msg(acpi, "ACPI not initialized.");
+    if (acpi->mcfg.alloc_num) {
+        // PCIe Enhanced Configuration Mechanism is supported.
+        // TODO: support PCIe addressing mechanism
+    }
+    // Otherwise, fallback to use legacy PCI 3.0 method.

     pci_probe();
 }
\ No newline at end of file
     pci_probe();
 }
\ No newline at end of file