update readme

[lunaix-os.git] / lunaix-os / hal / cpu.c

diff --git a/lunaix-os/hal/cpu.c b/lunaix-os/hal/cpu.c
index b2ef65704e00512b7a31652f3130fc0e78e3ffe6..ab5432c9642402556c0282eb8f0ee5982d22d9fb 100644 (file)
--- a/lunaix-os/hal/cpu.c
+++ b/lunaix-os/hal/cpu.c
@@ -4,7 +4,7 @@
 
 void cpu_get_model(char* model_out) {
     uint32_t* out = (uint32_t*)model_out;
-    reg32 eax, ebx, edx, ecx;
+    reg32 eax = 0, ebx = 0, edx = 0, ecx = 0;
     
     __get_cpuid(0, &eax, &ebx, &ecx, &edx);
 
@@ -27,7 +27,7 @@ void cpu_get_brand(char* brand_out) {
         brand_out[1] = '\0';
     }
     uint32_t* out = (uint32_t*) brand_out;
-    reg32 eax, ebx, edx, ecx;
+    reg32 eax = 0, ebx = 0, edx = 0, ecx = 0;
     for (uint32_t i = 2, j = 0; i < 5; i++)
     {
         __get_cpuid(BRAND_LEAF + i, &eax, &ebx, &ecx, &edx);
@@ -40,37 +40,28 @@ void cpu_get_brand(char* brand_out) {
     brand_out[48] = '\0';
 }
 
-reg32 cpu_r_cr0() {
-    asm volatile ("mov %cr0, %eax");
-}
-
-reg32 cpu_r_cr2() {
-    asm volatile ("mov %cr2, %eax");
-}
-
-reg32 cpu_r_cr3() {
-    asm volatile ("mov %cr3, %eax");
-}
 
-void cpu_w_cr0(reg32 v) {
-    asm volatile (
-        "mov %0, %%cr0"
-        :: "r"(v)
-    );
+int
+cpu_has_apic() {
+    // reference: Intel manual, section 10.4.2
+    reg32 eax = 0, ebx = 0, edx = 0, ecx = 0;
+    __get_cpuid(1, &eax, &ebx, &ecx, &edx);
+    
+    return (edx & 0x100);
 }
 
-void cpu_w_cr2(reg32 v) {
-    asm volatile (
-        "mov %0, %%cr2"
-        :: "r"(v)
-    );
-}
+void
+cpu_rdmsr(uint32_t msr_idx, uint32_t* reg_high, uint32_t* reg_low)
+{
+    uint32_t h = 0, l = 0;
+    asm volatile("rdmsr" : "=d"(h), "=a"(l) : "c"(msr_idx));
 
-void cpu_w_cr3(reg32 v) {
-    asm volatile (
-        "mov %0, %%cr3"
-        :: "r"(v)
-    );
+    *reg_high = h;
+    *reg_low = l;
 }
 
-
+void
+cpu_wrmsr(uint32_t msr_idx, uint32_t reg_high, uint32_t reg_low)
+{
+    asm volatile("wrmsr" : : "d"(reg_high), "a"(reg_low), "c"(msr_idx));
+}
\ No newline at end of file