Decoupling Architectural-specific Code (#35)

[lunaix-os.git] / lunaix-os / includes / hal / pci.h

diff --git a/lunaix-os/includes/hal/pci.h b/lunaix-os/includes/hal/pci.h
index b31352b3428bec4653cd6e89f0d79a5c07f9d242..da450906870f2c88a38578e9dd6eda0c51a25340 100644 (file)
--- a/lunaix-os/includes/hal/pci.h
+++ b/lunaix-os/includes/hal/pci.h
@@ -1,11 +1,17 @@
 #ifndef __LUNAIX_PCI_H
 #define __LUNAIX_PCI_H
 
 #ifndef __LUNAIX_PCI_H
 #define __LUNAIX_PCI_H
 

-#include <hal/io.h>
+#include <lunaix/device.h>
+#include <lunaix/ds/ldga.h>

 #include <lunaix/ds/llist.h>
 #include <lunaix/ds/llist.h>

+#include <lunaix/types.h>

 
 

-#define PCI_CONFIG_ADDR 0xcf8
-#define PCI_CONFIG_DATA 0xcfc
+#define EXPORT_PCI_DEVICE(id, pci_devdef, stage)                               \
+    EXPORT_DEVICE(id, &(pci_devdef)->devdef, stage)
+
+#define PCI_MATCH_EXACT -1
+#define PCI_MATCH_ANY 0
+#define PCI_MATCH_VENDOR 0xffff

 
 #define PCI_TDEV 0x0
 #define PCI_TPCIBRIDGE 0x1
 
 #define PCI_TDEV 0x0
 #define PCI_TPCIBRIDGE 0x1


@@ -17,24 +23,30 @@
 #define PCI_REG_STATUS_CMD 0x4
 #define PCI_REG_BAR(num) (0x10 + (num - 1) * 4)
 
 #define PCI_REG_STATUS_CMD 0x4
 #define PCI_REG_BAR(num) (0x10 + (num - 1) * 4)
 

-#define PCI_DEV_VENDOR(x) ((x)&0xffff)
-#define PCI_DEV_DEVID(x) ((x) >> 16)
-#define PCI_INTR_IRQ(x) ((x)&0xff)
-#define PCI_INTR_PIN(x) (((x)&0xff00) >> 8)
+#define PCI_DEV_VENDOR(x) ((x) & 0xffff)
+#define PCI_DEV_DEVID(x) (((x) & 0xffff0000) >> 16)
+#define PCI_INTR_IRQ(x) ((x) & 0xff)
+#define PCI_INTR_PIN(x) (((x) & 0xff00) >> 8)

 #define PCI_DEV_CLASS(x) ((x) >> 8)
 #define PCI_DEV_CLASS(x) ((x) >> 8)

-#define PCI_DEV_REV(x) (((x)&0xff))
+#define PCI_DEV_REV(x) (((x) & 0xff))

 #define PCI_BUS_NUM(x) (((x) >> 16) & 0xff)
 #define PCI_SLOT_NUM(x) (((x) >> 11) & 0x1f)
 #define PCI_FUNCT_NUM(x) (((x) >> 8) & 0x7)
 
 #define PCI_BUS_NUM(x) (((x) >> 16) & 0xff)
 #define PCI_SLOT_NUM(x) (((x) >> 11) & 0x1f)
 #define PCI_FUNCT_NUM(x) (((x) >> 8) & 0x7)
 

-#define PCI_BAR_MMIO(x) (!((x)&0x1))
-#define PCI_BAR_CACHEABLE(x) ((x)&0x8)
-#define PCI_BAR_TYPE(x) ((x)&0x6)
+#define PCI_BAR_MMIO(x) (!((x) & 0x1))
+#define PCI_BAR_CACHEABLE(x) ((x) & 0x8)
+#define PCI_BAR_TYPE(x) ((x) & 0x6)

 #define PCI_BAR_ADDR_MM(x) ((x) & ~0xf)
 #define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)
 
 #define PCI_BAR_ADDR_MM(x) ((x) & ~0xf)
 #define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)
 

-#define PCI_MSI_ADDR(msi_base) ((msi_base) + 4)
-#define PCI_MSI_DATA(msi_base) ((msi_base) + 8)
+#define PCI_MSI_ADDR_LO(msi_base) ((msi_base) + 4)
+#define PCI_MSI_ADDR_HI(msi_base) ((msi_base) + 8)
+#define PCI_MSI_DATA(msi_base, offset) ((msi_base) + 8 + offset)
+#define PCI_MSI_MASK(msi_base, offset) ((msi_base) + 0xc + offset)
+
+#define MSI_CAP_64BIT 0x80
+#define MSI_CAP_MASK 0x100
+#define MSI_CAP_ENABLE 0x1

 
 #define PCI_RCMD_DISABLE_INTR (1 << 10)
 #define PCI_RCMD_FAST_B2B (1 << 9)
 
 #define PCI_RCMD_DISABLE_INTR (1 << 10)
 #define PCI_RCMD_FAST_B2B (1 << 9)


@@ -42,52 +54,77 @@
 #define PCI_RCMD_MM_ACCESS (1 << 1)
 #define PCI_RCMD_IO_ACCESS 1
 
 #define PCI_RCMD_MM_ACCESS (1 << 1)
 #define PCI_RCMD_IO_ACCESS 1
 

-#define PCI_ADDRESS(bus, dev, funct)                                           \
-    (((bus)&0xff) << 16) | (((dev)&0xff) << 11) | (((funct)&0xff) << 8) |      \
-      0x80000000
+#define PCI_CFGADDR(pciloc) ((u32_t)(pciloc) << 8) | 0x80000000UL
+
+#define PCILOC(bus, dev, funct)                                                \
+    (((bus) & 0xff) << 8) | (((dev) & 0x1f) << 3) | ((funct) & 0x7)
+#define PCILOC_BUS(loc) (((loc) >> 8) & 0xff)
+#define PCILOC_DEV(loc) (((loc) >> 3) & 0x1f)
+#define PCILOC_FN(loc) ((loc) & 0x7)
+
+#define PCI_ID_ANY (-1)

 
 typedef unsigned int pci_reg_t;
 
 typedef unsigned int pci_reg_t;

+typedef u16_t pciaddr_t;

 
 // PCI device header format
 // Ref: "PCI Local Bus Specification, Rev.3, Section 6.1"
 
 
 // PCI device header format
 // Ref: "PCI Local Bus Specification, Rev.3, Section 6.1"
 

+#define BAR_TYPE_MMIO 0x1
+#define BAR_TYPE_CACHABLE 0x2
+#define PCI_DRV_NAME_LEN 32
+
+struct pci_base_addr
+{
+    u32_t start;
+    u32_t size;
+    u32_t type;
+};
+

 struct pci_device
 {
 struct pci_device
 {

+    struct device dev;

     struct llist_header dev_chain;
     struct llist_header dev_chain;

-    uint32_t device_info;
-    uint32_t class_info;
-    uint32_t cspace_base;
-    uint32_t msi_loc;
-    uint16_t intr_info;
+    struct hlist_node dev_cache;
+
+    struct
+    {
+        struct device* dev;
+        struct device_def* def;
+    } binding;
+
+    pciaddr_t loc;
+    u16_t intr_info;
+    u32_t device_info;
+    u32_t class_info;
+    u32_t cspace_base;
+    u32_t msi_loc;
+    struct pci_base_addr bar[6];

 };
 };

+#define PCI_DEVICE(devbase) (container_of((devbase), struct pci_device, dev))

 
 

-// PCI Configuration Space (C-Space) r/w:
-//      Refer to "PCI Local Bus Specification, Rev.3, Section 3.2.2.3.2"
-
-inline pci_reg_t
-pci_read_cspace(uint32_t base, int offset)
+struct pci_device_list

 {
 {

-    io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
-    return io_inl(PCI_CONFIG_DATA);
-}
+    struct llist_header peers;
+    struct pci_device* pcidev;
+};

 
 

-inline void
-pci_write_cspace(uint32_t base, int offset, pci_reg_t data)
-{
-    io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
-    io_outl(PCI_CONFIG_DATA, data);
-}
+typedef void* (*pci_drv_init)(struct pci_device*);

 
 

-/**
- * @brief 初始化PCI。这主要是通过扫描PCI总线进行拓扑重建。注意，该
- * 初始化不包括针对每个设备的初始化，因为那是设备驱动的事情。
- *
- */
-void
-pci_init();
+#define PCI_DEVIDENT(vendor, id)                                               \
+    ((((id) & 0xffff) << 16) | (((vendor) & 0xffff)))

 
 

-void
-pci_print_device();
+struct pci_device_def
+{
+    u32_t dev_class;
+    u32_t dev_ident;
+    u32_t ident_mask;
+    struct device_def devdef;
+};
+#define pcidev_def(dev_def_ptr)                                                \
+    container_of((dev_def_ptr), struct pci_device_def, devdef)
+
+#define binded_pcidev(pcidev) ((pcidev)->binding.def)

 
 /**
  * @brief 根据类型代码（Class Code）去在拓扑中寻找一个设备
 
 /**
  * @brief 根据类型代码（Class Code）去在拓扑中寻找一个设备


@@ -95,7 +132,7 @@ pci_print_device();
  *
  * @return struct pci_device*
  */
  *
  * @return struct pci_device*
  */

-struct pci_device* pci_get_device_by_class(uint32_t class);
+struct pci_device* pci_get_device_by_class(u32_t class);

 
 /**
  * @brief 根据设备商ID和设备ID，在拓扑中寻找一个设备
 
 /**
  * @brief 根据设备商ID和设备ID，在拓扑中寻找一个设备


@@ -105,7 +142,7 @@ struct pci_device* pci_get_device_by_class(uint32_t class);
  * @return struct pci_device*
  */
 struct pci_device*
  * @return struct pci_device*
  */
 struct pci_device*

-pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId);
+pci_get_device_by_id(u16_t vendorId, u16_t deviceId);

 
 /**
  * @brief 初始化PCI设备的基地址寄存器。返回由该基地址代表的，
 
 /**
  * @brief 初始化PCI设备的基地址寄存器。返回由该基地址代表的，


@@ -118,17 +155,30 @@ pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId);
  * @return size_t
  */
 size_t
  * @return size_t
  */
 size_t

-pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num);
+pci_bar_sizing(struct pci_device* dev, u32_t* bar_out, u32_t bar_num);

 
 /**
 
 /**

- * @brief 配置并启用设备MSI支持。
- * 参阅：PCI LB Spec. (Rev 3) Section 6.8 & 6.8.1
- * 以及：Intel Manual, Vol 3, Section 10.11
+ * @brief Bind an abstract device instance to the pci device

  *
  *

- * @param device PCI device
- * @param vector interrupt vector.
+ * @param pcidev pci device
+ * @param devobj abstract device instance

  */
  */

+void
+pci_bind_instance(struct pci_device* pcidev, void* devobj);
+
+void
+pci_probe_bar_info(struct pci_device* device);
+

 void
 pci_setup_msi(struct pci_device* device, int vector);
 
 void
 pci_setup_msi(struct pci_device* device, int vector);
 

+void
+pci_probe_msi_info(struct pci_device* device);
+
+int
+pci_bind_definition(struct pci_device_def* pcidev_def, int* more);
+
+int
+pci_bind_definition_all(struct pci_device_def* pcidef);
+

 #endif /* __LUNAIX_PCI_H */
 #endif /* __LUNAIX_PCI_H */