feat: gfxm: a layer provides user space access to low level interfacing of graphic...

[lunaix-os.git] / lunaix-os / includes / hal / pci.h

diff --git a/lunaix-os/includes/hal/pci.h b/lunaix-os/includes/hal/pci.h
index 186c6773aadfadafc16875319817e4b4232fc601..8c18997bc4fc14f0b96f278e70968c17557d5241 100644 (file)
--- a/lunaix-os/includes/hal/pci.h
+++ b/lunaix-os/includes/hal/pci.h
@@ -6,6 +6,13 @@
 #include <lunaix/ds/llist.h>
 #include <lunaix/types.h>
 
 #include <lunaix/ds/llist.h>
 #include <lunaix/types.h>
 

+#define EXPORT_PCI_DEVICE(id, pci_devdef)                                      \
+    EXPORT_DEVICE(id, &(pci_devdef)->devdef, load_pci_probe)
+
+#define PCI_MATCH_EXACT -1
+#define PCI_MATCH_ANY 0
+#define PCI_MATCH_VENDOR 0xffff
+

 #define PCI_TDEV 0x0
 #define PCI_TPCIBRIDGE 0x1
 #define PCI_TCARDBRIDGE 0x2
 #define PCI_TDEV 0x0
 #define PCI_TPCIBRIDGE 0x1
 #define PCI_TCARDBRIDGE 0x2


@@ -16,19 +23,19 @@
 #define PCI_REG_STATUS_CMD 0x4
 #define PCI_REG_BAR(num) (0x10 + (num - 1) * 4)
 
 #define PCI_REG_STATUS_CMD 0x4
 #define PCI_REG_BAR(num) (0x10 + (num - 1) * 4)
 

-#define PCI_DEV_VENDOR(x) ((x)&0xffff)
-#define PCI_DEV_DEVID(x) (((x)&0xffff0000) >> 16)
-#define PCI_INTR_IRQ(x) ((x)&0xff)
-#define PCI_INTR_PIN(x) (((x)&0xff00) >> 8)
+#define PCI_DEV_VENDOR(x) ((x) & 0xffff)
+#define PCI_DEV_DEVID(x) (((x) & 0xffff0000) >> 16)
+#define PCI_INTR_IRQ(x) ((x) & 0xff)
+#define PCI_INTR_PIN(x) (((x) & 0xff00) >> 8)

 #define PCI_DEV_CLASS(x) ((x) >> 8)
 #define PCI_DEV_CLASS(x) ((x) >> 8)

-#define PCI_DEV_REV(x) (((x)&0xff))
+#define PCI_DEV_REV(x) (((x) & 0xff))

 #define PCI_BUS_NUM(x) (((x) >> 16) & 0xff)
 #define PCI_SLOT_NUM(x) (((x) >> 11) & 0x1f)
 #define PCI_FUNCT_NUM(x) (((x) >> 8) & 0x7)
 
 #define PCI_BUS_NUM(x) (((x) >> 16) & 0xff)
 #define PCI_SLOT_NUM(x) (((x) >> 11) & 0x1f)
 #define PCI_FUNCT_NUM(x) (((x) >> 8) & 0x7)
 

-#define PCI_BAR_MMIO(x) (!((x)&0x1))
-#define PCI_BAR_CACHEABLE(x) ((x)&0x8)
-#define PCI_BAR_TYPE(x) ((x)&0x6)
+#define PCI_BAR_MMIO(x) (!((x) & 0x1))
+#define PCI_BAR_CACHEABLE(x) ((x) & 0x8)
+#define PCI_BAR_TYPE(x) ((x) & 0x6)

 #define PCI_BAR_ADDR_MM(x) ((x) & ~0xf)
 #define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)
 
 #define PCI_BAR_ADDR_MM(x) ((x) & ~0xf)
 #define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)
 


@@ -47,8 +54,8 @@
 #define PCI_RCMD_IO_ACCESS 1
 
 #define PCI_ADDRESS(bus, dev, funct)                                           \
 #define PCI_RCMD_IO_ACCESS 1
 
 #define PCI_ADDRESS(bus, dev, funct)                                           \

-    (((bus)&0xff) << 16) | (((dev)&0xff) << 11) | (((funct)&0xff) << 8) |      \
-      0x80000000
+    (((bus) & 0xff) << 16) | (((dev) & 0xff) << 11) |                          \
+      (((funct) & 0xff) << 8) | 0x80000000

 
 #define PCI_ID_ANY (-1)
 
 
 #define PCI_ID_ANY (-1)
 


@@ -79,14 +86,18 @@ struct pci_device
     u16_t intr_info;
     struct pci_base_addr bar[6];
 };
     u16_t intr_info;
     struct pci_base_addr bar[6];
 };

+#define PCI_DEVICE(devbase) (container_of((devbase), struct pci_device, dev))

 
 typedef void* (*pci_drv_init)(struct pci_device*);
 
 
 typedef void* (*pci_drv_init)(struct pci_device*);
 

+#define PCI_DEVIDENT(vendor, id)                                               \
+    ((((id) & 0xffff) << 16) | (((vendor) & 0xffff)))
+

 struct pci_device_def
 {
     u32_t dev_class;
 struct pci_device_def
 {
     u32_t dev_class;

-    u32_t dev_vendor;
-    u32_t dev_id;
+    u32_t dev_ident;
+    u32_t ident_mask;

     struct device_def devdef;
 };
 
     struct device_def devdef;
 };