#include <lunaix/block.h>
#include <lunaix/isrm.h>
#include <lunaix/mm/mmio.h>
-#include <lunaix/mm/pmm.h>
#include <lunaix/mm/valloc.h>
-#include <lunaix/mm/vmm.h>
+#include <lunaix/mm/page.h>
#include <lunaix/spike.h>
#include <lunaix/syslog.h>
#define HBA_CLB_SIZE 1024
#define HBA_MY_IE (HBA_PxINTR_DHR | HBA_PxINTR_TFE | HBA_PxINTR_OF)
+#define AHCI_DEVCLASS DEVCLASS(DEVIF_PCI, DEVFN_STORAGE, DEV_SATA)
// #define DO_HBA_FULL_RESET
"SATA II (3.0Gbps)",
"SATA III (6.0Gbps)" };
-extern void
-ahci_fsexport(struct block_dev* bdev, void* fs_node);
+static struct devclass ahci_class = AHCI_DEVCLASS;
extern void
-__ahci_hba_isr(const isr_param* param);
+ahci_fsexport(struct block_dev* bdev, void* fs_node);
extern void
__ahci_blkio_handler(struct blkio_req* req);
port_reg[HBA_RPxSCTL] &= ~0xf;
}
-int
-ahci_driver_init(struct device_def* def, struct device* dev)
+struct ahci_driver*
+ahci_driver_init(struct ahci_driver_param* param)
{
- struct pci_device* ahci_dev = container_of(dev, struct pci_device, dev);
-
- struct pci_base_addr* bar6 = &ahci_dev->bar[5];
- assert_msg(bar6->type & BAR_TYPE_MMIO, "AHCI: BAR#6 is not MMIO.");
-
- pci_reg_t cmd = pci_read_cspace(ahci_dev->cspace_base, PCI_REG_STATUS_CMD);
-
- // 禁用传统中断(因为我们使用MSI),启用MMIO访问,允许PCI设备间访问
- cmd |= (PCI_RCMD_MM_ACCESS | PCI_RCMD_DISABLE_INTR | PCI_RCMD_BUS_MASTER);
-
- pci_write_cspace(ahci_dev->cspace_base, PCI_REG_STATUS_CMD, cmd);
-
- int iv = isrm_ivexalloc(__ahci_hba_isr);
- pci_setup_msi(ahci_dev, iv);
- isrm_set_payload(iv, (ptr_t)&ahcis);
-
struct ahci_driver* ahci_drv = vzalloc(sizeof(*ahci_drv));
struct ahci_hba* hba = &ahci_drv->hba;
- ahci_drv->id = iv;
+ ahci_drv->id = param->ahci_iv;
+
+ isrm_set_payload(param->ahci_iv, (ptr_t)&ahcis);
llist_append(&ahcis, &ahci_drv->ahci_drvs);
- hba->base = (hba_reg_t*)ioremap(bar6->start, bar6->size);
+ hba->base = (hba_reg_t*)ioremap(param->mmio_base, param->mmio_size);
#ifdef DO_HBA_FULL_RESET
// 重置HBA
__hba_reset_port(port_regs);
#endif
+ struct leaflet* leaflet;
if (!clbp) {
// 每页最多4个命令队列
- clb_pa = pmm_alloc_page(KERNEL_PID, PP_FGLOCKED);
- clb_pg_addr = (ptr_t)ioremap(clb_pa, 0x1000);
+ leaflet = alloc_leaflet(0);
+ clb_pa = leaflet_addr(leaflet);
+ clb_pg_addr = vmap(leaflet, KERNEL_DATA);
memset((void*)clb_pg_addr, 0, 0x1000);
}
if (!fisp) {
// 每页最多16个FIS
- fis_pa = pmm_alloc_page(KERNEL_PID, PP_FGLOCKED);
- fis_pg_addr = (ptr_t)ioremap(fis_pa, 0x1000);
+ leaflet = alloc_leaflet(0);
+ fis_pa = leaflet_addr(leaflet);
+ fis_pg_addr = vmap(leaflet, KERNEL_DATA);
memset((void*)fis_pg_addr, 0, 0x1000);
}
port_regs[HBA_RPxCMD] |= HBA_PxCMD_ST;
if (!ahci_init_device(port)) {
- kprintf(KERROR "init fail: 0x%x@p%d\n", port->regs[HBA_RPxSIG], i);
+ ERROR("init fail: 0x%x@p%d", port->regs[HBA_RPxSIG], i);
continue;
}
struct hba_device* hbadev = port->device;
- kprintf(KINFO "sata%d: %s, blk_size=%d, blk=0..%d\n",
+ kprintf(KINFO "sata%d: %s, blk_size=%d, blk=0..%d",
i,
hbadev->model,
hbadev->block_size,
ahci_register_device(hbadev);
}
- dev->underlay = ahci_drv;
- return 0;
+ return ahci_drv;
}
void
bdev->end_lba = hbadev->max_lba;
bdev->blk_size = hbadev->block_size;
+ bdev->class = &ahci_class;
block_mount(bdev, ahci_fsexport);
}
port->device->ops.submit = scsi_submit;
}
}
-
-static struct pci_device_def ahcidef = {
- .dev_class = AHCI_HBA_CLASS,
- .dev_vendor = PCI_ID_ANY,
- .dev_id = PCI_ID_ANY,
- .devdef = { .class = DEVCLASS(DEVIF_PCI, DEVFN_STORAGE, DEV_SATA, 0),
- .name = "SATA AHCI",
- .init_for = ahci_driver_init }
-};
-EXPORT_DEVICE(ahci, &ahcidef.devdef, load_on_demand);
\ No newline at end of file