X-Git-Url: https://scm.lunaixsky.com/lunaix-os.git/blobdiff_plain/01a605198da7bc5883a3dfa96b38f4f7c04f67f9..45e1f8b055043e54be35462852ab6649d634da7c:/lunaix-os/includes/hal/pci.h

diff --git a/lunaix-os/includes/hal/pci.h b/lunaix-os/includes/hal/pci.h
index b31352b..b95f89a 100644
--- a/lunaix-os/includes/hal/pci.h
+++ b/lunaix-os/includes/hal/pci.h
@@ -3,6 +3,7 @@
 
 #include <hal/io.h>
 #include <lunaix/ds/llist.h>
+#include <lunaix/types.h>
 
 #define PCI_CONFIG_ADDR 0xcf8
 #define PCI_CONFIG_DATA 0xcfc
@@ -34,7 +35,12 @@
 #define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)
 
 #define PCI_MSI_ADDR(msi_base) ((msi_base) + 4)
-#define PCI_MSI_DATA(msi_base) ((msi_base) + 8)
+#define PCI_MSI_DATA(msi_base, offset) ((msi_base) + 8 + offset)
+#define PCI_MSI_MASK(msi_base, offset) ((msi_base) + 0xc + offset)
+
+#define MSI_CAP_64BIT 0x80
+#define MSI_CAP_MASK 0x100
+#define MSI_CAP_ENABLE 0x1
 
 #define PCI_RCMD_DISABLE_INTR (1 << 10)
 #define PCI_RCMD_FAST_B2B (1 << 9)
@@ -51,28 +57,58 @@ typedef unsigned int pci_reg_t;
 // PCI device header format
 // Ref: "PCI Local Bus Specification, Rev.3, Section 6.1"
 
+#define BAR_TYPE_MMIO 0x1
+#define BAR_TYPE_CACHABLE 0x2
+#define PCI_DRV_NAME_LEN 32
+
+struct pci_driver;
+
+struct pci_base_addr
+{
+    u32_t start;
+    u32_t size;
+    u32_t type;
+};
+
 struct pci_device
 {
     struct llist_header dev_chain;
-    uint32_t device_info;
-    uint32_t class_info;
-    uint32_t cspace_base;
-    uint32_t msi_loc;
-    uint16_t intr_info;
+    u32_t device_info;
+    u32_t class_info;
+    u32_t cspace_base;
+    u32_t msi_loc;
+    u16_t intr_info;
+    struct
+    {
+        struct pci_driver* type;
+        void* instance;
+    } driver;
+    struct pci_base_addr bar[6];
+};
+
+typedef void* (*pci_drv_init)(struct pci_device*);
+
+struct pci_driver
+{
+    struct llist_header drivers;
+    u32_t dev_info;
+    u32_t dev_class;
+    pci_drv_init create_driver;
+    char name[PCI_DRV_NAME_LEN];
 };
 
 // PCI Configuration Space (C-Space) r/w:
 //      Refer to "PCI Local Bus Specification, Rev.3, Section 3.2.2.3.2"
 
-inline pci_reg_t
-pci_read_cspace(uint32_t base, int offset)
+static inline pci_reg_t
+pci_read_cspace(u32_t base, int offset)
 {
     io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
     return io_inl(PCI_CONFIG_DATA);
 }
 
-inline void
-pci_write_cspace(uint32_t base, int offset, pci_reg_t data)
+static inline void
+pci_write_cspace(u32_t base, int offset, pci_reg_t data)
 {
     io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
     io_outl(PCI_CONFIG_DATA, data);
@@ -86,16 +122,13 @@ pci_write_cspace(uint32_t base, int offset, pci_reg_t data)
 void
 pci_init();
 
-void
-pci_print_device();
-
 /**
  * @brief 根据类型代码（Class Code）去在拓扑中寻找一个设备
  * 类型代码请参阅： PCI LB Spec. Appendix D.
  *
  * @return struct pci_device*
  */
-struct pci_device* pci_get_device_by_class(uint32_t class);
+struct pci_device* pci_get_device_by_class(u32_t class);
 
 /**
  * @brief 根据设备商ID和设备ID，在拓扑中寻找一个设备
@@ -105,7 +138,7 @@ struct pci_device* pci_get_device_by_class(uint32_t class);
  * @return struct pci_device*
  */
 struct pci_device*
-pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId);
+pci_get_device_by_id(u16_t vendorId, u16_t deviceId);
 
 /**
  * @brief 初始化PCI设备的基地址寄存器。返回由该基地址代表的，
@@ -118,7 +151,7 @@ pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId);
  * @return size_t
  */
 size_t
-pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num);
+pci_bar_sizing(struct pci_device* dev, u32_t* bar_out, u32_t bar_num);
 
 /**
  * @brief 配置并启用设备MSI支持。
@@ -131,4 +164,20 @@ pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num);
 void
 pci_setup_msi(struct pci_device* device, int vector);
 
+void
+pci_add_driver(const char* name,
+               u32_t class,
+               u32_t vendor,
+               u32_t devid,
+               pci_drv_init init);
+
+int
+pci_bind_driver(struct pci_device* pci_dev);
+
+void
+pci_probe_bar_info(struct pci_device* device);
+
+void
+pci_probe_msi_info(struct pci_device* device);
+
 #endif /* __LUNAIX_PCI_H */