X-Git-Url: https://scm.lunaixsky.com/lunaix-os.git/blobdiff_plain/1025235c72c31f7fa7b648c0e32ddcaa68a8f66a..9b840d9c5c0db5e621e475dc8414edd98497ed36:/lunaix-os/arch/LConfig

diff --git a/lunaix-os/arch/LConfig b/lunaix-os/arch/LConfig
index 30c67b6..1031636 100644
--- a/lunaix-os/arch/LConfig
+++ b/lunaix-os/arch/LConfig
@@ -1,13 +1,45 @@
-include("i386/LConfig")
+include("x86/LConfig")
+include("aarch64/LConfig")
 
-@Collection
+@Collection("Platform")
 def architecture_support():
     """
         Config ISA related features
     """
 
-    @Term
+    @Term("Architecture")
     def arch():
-        """ Config ISA support """
-        type(["i386", "x86_64", "aarch64", "rv64"])
-        default("i386")
+        """ 
+            Config ISA support 
+        """
+        # type(["i386", "x86_64", "aarch64", "rv64"])
+        type(["i386", "x86_64", "aarch64"])
+        default("x86_64")
+
+        env_val = env("ARCH")
+        if env_val:
+            set_value(env_val)
+
+    @Term("Base operand size")
+    @ReadOnly
+    def arch_bits():
+        """ 
+            Defines the base size of a general register of the 
+            current selected ISA.
+
+            This the 'bits' part when we are talking about a CPU
+        """
+
+        type(["64", "32"])
+        match v(arch):
+            case "i386": 
+                default("32")
+            case "aarch64": 
+                default("64")
+            case "rv64": 
+                default("64")
+            case "x86_64": 
+                default("64")
+            case _:
+                default("32")
+        
\ No newline at end of file