X-Git-Url: https://scm.lunaixsky.com/lunaix-os.git/blobdiff_plain/2236410f4582ab45ae8c384dd6eeeef5d10aab15..6942ebae59c3904674dce6b67cd07c43a3bbe00d:/lunaix-os/hal/ahci/ahci_pci.c?ds=sidebyside

diff --git a/lunaix-os/hal/ahci/ahci_pci.c b/lunaix-os/hal/ahci/ahci_pci.c
index 0ecde58..4435da1 100644
--- a/lunaix-os/hal/ahci/ahci_pci.c
+++ b/lunaix-os/hal/ahci/ahci_pci.c
@@ -1,51 +1,74 @@
 #include <lunaix/spike.h>
+#include <lunaix/status.h>
 
 #include <hal/ahci/ahci.h>
 #include <hal/pci.h>
-#include <sys/pci_hba.h>
 
 static int
-ahci_pci_bind(struct device_def* def, struct device* dev)
+ahci_pci_create(struct device_def* def, morph_t* morphed)
 {
-    struct pci_device* ahci_dev = container_of(dev, struct pci_device, dev);
+    struct pci_probe* probe;
+    struct device* dev;
+    struct pci_base_addr* bar6;
+    struct ahci_driver* ahci_drv;
+    msi_vector_t msiv;
 
-    struct pci_base_addr* bar6 = &ahci_dev->bar[5];
-    assert_msg(bar6->type & BAR_TYPE_MMIO, "AHCI: BAR#6 is not MMIO.");
+    probe = changeling_try_reveal(morphed, pci_probe_morpher);
+    if (!probe) {
+        return EINVAL;
+    }
 
-    pci_reg_t cmd = pci_read_cspace(ahci_dev->cspace_base, PCI_REG_STATUS_CMD);
+    bar6 = pci_device_bar(probe, 5);
+    assert_msg(pci_bar_mmio_space(bar6), "AHCI: BAR#6 is not MMIO.");
 
-    // 禁用传统中断（因为我们使用MSI），启用MMIO访问，允许PCI设备间访问
-    cmd |= (PCI_RCMD_MM_ACCESS | PCI_RCMD_DISABLE_INTR | PCI_RCMD_BUS_MASTER);
+    pci_reg_t cmd = 0;
+    pci_cmd_set_bus_master(&cmd);
+    pci_cmd_set_mmio(&cmd);
+    pci_cmd_set_msi(&cmd);
+    pci_apply_command(probe, cmd);
+    
+    assert(pci_capability_msi(probe));
 
-    pci_write_cspace(ahci_dev->cspace_base, PCI_REG_STATUS_CMD, cmd);
-
-    int iv = isrm_ivexalloc(ahci_hba_isr);
-    pci_setup_msi(ahci_dev, iv);
+    msiv = pci_msi_setup_simple(probe, ahci_hba_isr);
 
     struct ahci_driver_param param = {
         .mmio_base = bar6->start,
         .mmio_size = bar6->size,
-        .ahci_iv = iv,
+        .ahci_iv = msi_vect(msiv),
     };
 
-    struct ahci_driver* ahci_drv = ahci_driver_init(&param);
-    pci_bind_instance(ahci_dev, ahci_drv);
+    ahci_drv = ahci_driver_init(&param);
+    dev = device_allocvol(NULL, ahci_drv);
+
+    device_setname(dev_meta(dev), 
+                   "pci-ahci%d", devclass_mkvar(&def->class));
+
+    pci_bind_instance(probe, dev);
 
     return 0;
 }
 
+static bool
+ahci_pci_compat(struct pci_probe* probe)
+{
+    return pci_device_class(probe) == AHCI_HBA_CLASS;
+}
+
 static int
-ahci_pci_init(struct device_def* def)
+ahci_pci_register(struct device_def* def)
 {
-    return pci_bind_definition_all(pcidev_def(def));
+    return !pci_register_driver(def, ahci_pci_compat);
 }
 
-static struct pci_device_def ahcidef = {
-    .dev_class = AHCI_HBA_CLASS,
-    .ident_mask = PCI_MATCH_ANY,
-    .devdef = { .class = DEVCLASS(DEVIF_PCI, DEVFN_STORAGE, DEV_SATA),
-                .name = "Generic SATA",
-                .init = ahci_pci_init,
-                .bind = ahci_pci_bind }
+
+static struct device_def ahcidef = 
+{
+    def_device_class(GENERIC, STORAGE, SATA),
+    def_device_name("Generic AHCI (pci-bus)"),
+
+    def_on_register(ahci_pci_register),
+    def_on_create(ahci_pci_create),
+
+    def_non_trivial
 };
-EXPORT_PCI_DEVICE(ahci, &ahcidef, load_postboot);
\ No newline at end of file
+EXPORT_DEVICE(ahci, &ahcidef, load_postboot);
\ No newline at end of file