X-Git-Url: https://scm.lunaixsky.com/lunaix-os.git/blobdiff_plain/2803826a2373620dbfce8a5bff1e6a01dd594953..839da03f6ebe838d780e52190318d4c3048990f1:/lunaix-os/hal/apic.c

diff --git a/lunaix-os/hal/apic.c b/lunaix-os/hal/apic.c
index 289dd56..0099525 100644
--- a/lunaix-os/hal/apic.c
+++ b/lunaix-os/hal/apic.c
@@ -15,11 +15,14 @@
 
 #include <arch/x86/interrupts.h>
 
+#include <lunaix/mm/mmio.h>
 #include <lunaix/spike.h>
 #include <lunaix/syslog.h>
 
 LOG_MODULE("APIC")
 
+static volatile uintptr_t _apic_base;
+
 void
 apic_setup_lvts();
 
@@ -36,10 +39,12 @@ apic_init()
     // As we are going to use APIC, disable the old 8259 PIC
     pic_disable();
 
+    _apic_base = ioremap(__APIC_BASE_PADDR, 4096);
+
     // Hardware enable the APIC
     // By setting bit 11 of IA32_APIC_BASE register
-    // Note: After this point, you can't disable then re-enable it until a reset
-    // (i.e., reboot)
+    // Note: After this point, you can't disable then re-enable it until a
+    // reset (i.e., reboot)
     asm volatile("movl %0, %%ecx\n"
                  "rdmsr\n"
                  "orl %1, %%eax\n"
@@ -91,3 +96,21 @@ apic_setup_lvts()
     apic_write_reg(APIC_LVT_LINT1, LVT_ENTRY_LINT1);
     apic_write_reg(APIC_LVT_ERROR, LVT_ENTRY_ERROR(APIC_ERROR_IV));
 }
+
+void
+apic_done_servicing()
+{
+    *(unsigned int*)(_apic_base + APIC_EOI) = 0;
+}
+
+unsigned int
+apic_read_reg(unsigned int reg)
+{
+    return *(unsigned int*)(_apic_base + (reg));
+}
+
+void
+apic_write_reg(unsigned int reg, unsigned int val)
+{
+    *(unsigned int*)(_apic_base + reg) = val;
+}
\ No newline at end of file