X-Git-Url: https://scm.lunaixsky.com/lunaix-os.git/blobdiff_plain/28c176b668c841a3b7fb093faccf0efa39257603..2bfb909dde1241111ab5568f30c45d2644bdaf25:/lunaix-os/arch/LConfig diff --git a/lunaix-os/arch/LConfig b/lunaix-os/arch/LConfig index 22f96c0..bb22a10 100644 --- a/lunaix-os/arch/LConfig +++ b/lunaix-os/arch/LConfig @@ -1,34 +1,51 @@ -include("x86/LConfig") +from . import x86 -@Collection +@"Platform" def architecture_support(): """ Config ISA related features """ - @Term - def arch(): - """ Config ISA support """ - type(["i386", "x86_64", "aarch64", "rv64"]) - default("i386") + @flag + def arch_x86_32() -> bool: + when(arch is "i386") + + @flag + def arch_x86_64() -> bool: + when(arch is "x86_64") + + @flag + def arch_x86() -> bool: + when(arch is "i386") + when(arch is "x86_64") - env_val = env("ARCH") - if env_val is not None: - set_value(env_val) + @"Architecture" + def arch() -> "i386" | "x86_64": + """ + Config ISA support + """ + _arch = env("ARCH") + return _arch if _arch else "x86_64" - @Term - @ReadOnly - def arch_bits(): - type(["64", "32"]) - match v(arch): + @"Base operand size" + @readonly + def arch_bits() -> 32 | 64: + """ + Defines the base size of a general register of the + current selected ISA. + + This the 'bits' part when we are talking about a CPU + """ + + match arch.val: case "i386": - default("32") + return 32 case "aarch64": - default("64") + return 64 case "rv64": - default("64") + return 64 case "x86_64": - default("64") + return 64 case _: - default("32") + return 32 \ No newline at end of file