X-Git-Url: https://scm.lunaixsky.com/lunaix-os.git/blobdiff_plain/423c98c95abf756e6982c51fd7757dcb67f3f9ea..bb7ce16533fb6c1384775dea6e1150e74c229daf:/lunaix-os/hal/pci.c diff --git a/lunaix-os/hal/pci.c b/lunaix-os/hal/pci.c index 90011c6..ca31e21 100644 --- a/lunaix-os/hal/pci.c +++ b/lunaix-os/hal/pci.c @@ -1,5 +1,19 @@ +/** + * @file pci.c + * @author Lunaixsky (zelong56@gmail.com) + * @brief A software implementation of PCI Local Bus Specification Revision 3.0 + * @version 0.1 + * @date 2022-06-28 + * + * @copyright Copyright (c) 2022 + * + */ +#include +#include #include -#include +#include +#include +#include #include LOG_MODULE("PCI") @@ -23,7 +37,10 @@ pci_probe_device(int bus, int dev, int funct) pci_reg_t hdr_type = pci_read_cspace(base, 0xc); hdr_type = (hdr_type >> 16) & 0xff; - if ((hdr_type & 0x80)) { + // 防止堆栈溢出 + // QEMU的ICH9/Q35实现似乎有点问题，对于多功能设备的每一个功能的header type + // 都将第七位置位。而virtualbox 就没有这个毛病。 + if ((hdr_type & 0x80) && funct == 0) { hdr_type = hdr_type & ~0x80; // 探测多用途设备（multi-function device） for (int i = 1; i < 7; i++) { @@ -31,7 +48,7 @@ pci_probe_device(int bus, int dev, int funct) } } - if (hdr_type != 0) { + if (hdr_type != PCI_TDEV) { // XXX: 目前忽略所有桥接设备，比如PCI-PCI桥接器，或者是CardBus桥接器 return; } @@ -39,7 +56,7 @@ pci_probe_device(int bus, int dev, int funct) pci_reg_t intr = pci_read_cspace(base, 0x3c); pci_reg_t class = pci_read_cspace(base, 0x8); - struct pci_device* device = lxmalloc(sizeof(struct pci_device)); + struct pci_device* device = valloc(sizeof(struct pci_device)); *device = (struct pci_device){ .cspace_base = base, .class_info = class, .device_info = reg1, @@ -65,6 +82,9 @@ pci_probe() void pci_probe_msi_info(struct pci_device* device) { + // Note that Virtualbox have to use ICH9 chipset for MSI support. + // Qemu seems ok with default PIIX3, Bochs is pending to test... + // See https://www.virtualbox.org/manual/ch03.html (section 3.5.1) pci_reg_t status = pci_read_cspace(device->cspace_base, PCI_REG_STATUS_CMD) >> 16; @@ -87,30 +107,95 @@ pci_probe_msi_info(struct pci_device* device) } } +#define PCI_PRINT_BAR_LISTING + +int +__pci_read_cspace(struct v_inode* inode, void* buffer, size_t len, size_t fpos) +{ + if (len < 256) { + return ERANGE; + } + + struct twifs_node* node = (struct twifs_node*)(inode->data); + struct pci_device* pcidev = (struct pci_device*)(node->data); + + for (size_t i = 0; i < 256; i += sizeof(pci_reg_t)) { + *(pci_reg_t*)(buffer + i) = pci_read_cspace(pcidev->cspace_base, i); + } + + return 256; +} + void -pci_print_device() +pci_build_fsmapping() { + struct twifs_node *pci_class = twifs_dir_node(NULL, "pci"), *pci_dev; struct pci_device *pos, *n; llist_for_each(pos, n, &pci_devices, dev_chain) { - kprintf(KINFO "(B%xh:D%xh:F%xh) Dev %x:%x, Class 0x%x\n", - PCI_BUS_NUM(pos->cspace_base), - PCI_SLOT_NUM(pos->cspace_base), - PCI_FUNCT_NUM(pos->cspace_base), - PCI_DEV_VENDOR(pos->device_info), - PCI_DEV_DEVID(pos->device_info), - PCI_DEV_CLASS(pos->class_info)); - - kprintf(KINFO "\t IRQ: %d, INT#x: %d\n", - PCI_INTR_IRQ(pos->intr_info), - PCI_INTR_PIN(pos->intr_info)); - - if (pos->msi_loc) { - kprintf(KINFO "\t MSI supported (@%xh)\n", pos->msi_loc); - } + pci_dev = twifs_dir_node(pci_class, + "B%d:D%d:F%d.%x:%x", + PCI_BUS_NUM(pos->cspace_base), + PCI_SLOT_NUM(pos->cspace_base), + PCI_FUNCT_NUM(pos->cspace_base), + PCI_DEV_VENDOR(pos->device_info), + PCI_DEV_DEVID(pos->device_info)); + struct twifs_node* fnode = twifs_file_node(pci_dev, "cspace"); + fnode->data = pos; + fnode->ops.read = __pci_read_cspace; } } +size_t +pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num) +{ + pci_reg_t bar = pci_read_cspace(dev->cspace_base, PCI_REG_BAR(bar_num)); + if (!bar) { + *bar_out = 0; + return 0; + } + + pci_write_cspace(dev->cspace_base, PCI_REG_BAR(bar_num), 0xffffffff); + pci_reg_t sized = + pci_read_cspace(dev->cspace_base, PCI_REG_BAR(bar_num)) & ~0x1; + if (PCI_BAR_MMIO(bar)) { + sized = PCI_BAR_ADDR_MM(sized); + } + *bar_out = bar; + pci_write_cspace(dev->cspace_base, PCI_REG_BAR(bar_num), bar); + return ~sized + 1; +} + +void +pci_setup_msi(struct pci_device* device, int vector) +{ + // Dest: APIC#0, Physical Destination, No redirection + uint32_t msi_addr = (__APIC_BASE_PADDR); + + // Edge trigger, Fixed delivery + uint32_t msi_data = vector; + + pci_write_cspace( + device->cspace_base, PCI_MSI_ADDR(device->msi_loc), msi_addr); + + pci_reg_t reg1 = pci_read_cspace(device->cspace_base, device->msi_loc); + pci_reg_t msg_ctl = reg1 >> 16; + + int offset = !!(msg_ctl & MSI_CAP_64BIT) * 4; + pci_write_cspace(device->cspace_base, + PCI_MSI_DATA(device->msi_loc, offset), + msi_data & 0xffff); + + if ((msg_ctl & MSI_CAP_MASK)) { + pci_write_cspace( + device->cspace_base, PCI_MSI_MASK(device->msi_loc, offset), 0); + } + + // manipulate the MSI_CTRL to allow device using MSI to request service. + reg1 = (reg1 & 0xff8fffff) | 0x10000; + pci_write_cspace(device->cspace_base, device->msi_loc, reg1); +} + struct pci_device* pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId) { @@ -144,5 +229,14 @@ void pci_init() { llist_init_head(&pci_devices); + acpi_context* acpi = acpi_get_context(); + assert_msg(acpi, "ACPI not initialized."); + if (acpi->mcfg.alloc_num) { + // PCIe Enhanced Configuration Mechanism is supported. + // TODO: support PCIe addressing mechanism + } + // Otherwise, fallback to use legacy PCI 3.0 method. pci_probe(); + + pci_build_fsmapping(); } \ No newline at end of file