X-Git-Url: https://scm.lunaixsky.com/lunaix-os.git/blobdiff_plain/45e1f8b055043e54be35462852ab6649d634da7c..f89517343bf062d299d54408eea2f9387bfefb6d:/lunaix-os/includes/hal/pci.h

diff --git a/lunaix-os/includes/hal/pci.h b/lunaix-os/includes/hal/pci.h
index b95f89a..22b3dd9 100644
--- a/lunaix-os/includes/hal/pci.h
+++ b/lunaix-os/includes/hal/pci.h
@@ -1,16 +1,14 @@
 #ifndef __LUNAIX_PCI_H
 #define __LUNAIX_PCI_H
 
-#include <hal/io.h>
+#include <lunaix/device.h>
+#include <lunaix/ds/ldga.h>
 #include <lunaix/ds/llist.h>
+#include <lunaix/ds/hashtable.h>
 #include <lunaix/types.h>
+#include <lunaix/changeling.h>
 
-#define PCI_CONFIG_ADDR 0xcf8
-#define PCI_CONFIG_DATA 0xcfc
-
-#define PCI_TDEV 0x0
-#define PCI_TPCIBRIDGE 0x1
-#define PCI_TCARDBRIDGE 0x2
+#include "irq.h"
 
 #define PCI_VENDOR_INVLD 0xffff
 
@@ -18,23 +16,25 @@
 #define PCI_REG_STATUS_CMD 0x4
 #define PCI_REG_BAR(num) (0x10 + (num - 1) * 4)
 
-#define PCI_DEV_VENDOR(x) ((x)&0xffff)
-#define PCI_DEV_DEVID(x) ((x) >> 16)
-#define PCI_INTR_IRQ(x) ((x)&0xff)
-#define PCI_INTR_PIN(x) (((x)&0xff00) >> 8)
+#define PCI_DEV_VENDOR(x) ((x) & 0xffff)
+#define PCI_DEV_DEVID(x) (((x) & 0xffff0000) >> 16)
+#define PCI_INTR_IRQ(x) ((x) & 0xff)
+#define PCI_INTR_PIN(x) (((x) & 0xff00) >> 8)
 #define PCI_DEV_CLASS(x) ((x) >> 8)
-#define PCI_DEV_REV(x) (((x)&0xff))
+#define PCI_DEV_REV(x) (((x) & 0xff))
 #define PCI_BUS_NUM(x) (((x) >> 16) & 0xff)
 #define PCI_SLOT_NUM(x) (((x) >> 11) & 0x1f)
 #define PCI_FUNCT_NUM(x) (((x) >> 8) & 0x7)
 
-#define PCI_BAR_MMIO(x) (!((x)&0x1))
-#define PCI_BAR_CACHEABLE(x) ((x)&0x8)
-#define PCI_BAR_TYPE(x) ((x)&0x6)
+#define PCI_BAR_MMIO(x) (!((x) & 0x1))
+#define PCI_BAR_CACHEABLE(x) ((x) & 0x8)
+#define PCI_BAR_TYPE(x) ((x) & 0x6)
 #define PCI_BAR_ADDR_MM(x) ((x) & ~0xf)
 #define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)
+#define PCI_BAR_COUNT 6
 
-#define PCI_MSI_ADDR(msi_base) ((msi_base) + 4)
+#define PCI_MSI_ADDR_LO(msi_base) ((msi_base) + 4)
+#define PCI_MSI_ADDR_HI(msi_base) ((msi_base) + 8)
 #define PCI_MSI_DATA(msi_base, offset) ((msi_base) + 8 + offset)
 #define PCI_MSI_MASK(msi_base, offset) ((msi_base) + 0xc + offset)
 
@@ -48,11 +48,16 @@
 #define PCI_RCMD_MM_ACCESS (1 << 1)
 #define PCI_RCMD_IO_ACCESS 1
 
-#define PCI_ADDRESS(bus, dev, funct)                                           \
-    (((bus)&0xff) << 16) | (((dev)&0xff) << 11) | (((funct)&0xff) << 8) |      \
-      0x80000000
+#define PCI_CFGADDR(pciloc) ((u32_t)(pciloc) << 8) | 0x80000000UL
+
+#define PCILOC(bus, dev, funct)                                                \
+    (((bus) & 0xff) << 8) | (((dev) & 0x1f) << 3) | ((funct) & 0x7)
+#define PCILOC_BUS(loc) (((loc) >> 8) & 0xff)
+#define PCILOC_DEV(loc) (((loc) >> 3) & 0x1f)
+#define PCILOC_FN(loc) ((loc) & 0x7)
 
 typedef unsigned int pci_reg_t;
+typedef u16_t pciaddr_t;
 
 // PCI device header format
 // Ref: "PCI Local Bus Specification, Rev.3, Section 6.1"
@@ -61,8 +66,6 @@ typedef unsigned int pci_reg_t;
 #define BAR_TYPE_CACHABLE 0x2
 #define PCI_DRV_NAME_LEN 32
 
-struct pci_driver;
-
 struct pci_base_addr
 {
     u32_t start;
@@ -70,75 +73,35 @@ struct pci_base_addr
     u32_t type;
 };
 
-struct pci_device
+struct pci_probe
 {
-    struct llist_header dev_chain;
+    morph_t mobj;
+
+    pciaddr_t loc;
+    u16_t intr_info;
     u32_t device_info;
     u32_t class_info;
     u32_t cspace_base;
     u32_t msi_loc;
-    u16_t intr_info;
-    struct
-    {
-        struct pci_driver* type;
-        void* instance;
-    } driver;
     struct pci_base_addr bar[6];
-};
-
-typedef void* (*pci_drv_init)(struct pci_device*);
 
-struct pci_driver
-{
-    struct llist_header drivers;
-    u32_t dev_info;
-    u32_t dev_class;
-    pci_drv_init create_driver;
-    char name[PCI_DRV_NAME_LEN];
+    struct device* bind;
+    struct irq_domain* irq_domain;
 };
+#define pci_probe_morpher   morphable_attrs(pci_probe, mobj)
 
-// PCI Configuration Space (C-Space) r/w:
-//      Refer to "PCI Local Bus Specification, Rev.3, Section 3.2.2.3.2"
-
-static inline pci_reg_t
-pci_read_cspace(u32_t base, int offset)
-{
-    io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
-    return io_inl(PCI_CONFIG_DATA);
-}
+typedef bool (*pci_id_checker_t)(struct pci_probe*);
 
-static inline void
-pci_write_cspace(u32_t base, int offset, pci_reg_t data)
+struct pci_registry
 {
-    io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
-    io_outl(PCI_CONFIG_DATA, data);
-}
-
-/**
- * @brief 初始化PCI。这主要是通过扫描PCI总线进行拓扑重建。注意，该
- * 初始化不包括针对每个设备的初始化，因为那是设备驱动的事情。
- *
- */
-void
-pci_init();
+    struct hlist_node entries;
+    struct device_def* definition;
 
-/**
- * @brief 根据类型代码（Class Code）去在拓扑中寻找一个设备
- * 类型代码请参阅： PCI LB Spec. Appendix D.
- *
- * @return struct pci_device*
- */
-struct pci_device* pci_get_device_by_class(u32_t class);
+    pci_id_checker_t check_compact;
+};
 
-/**
- * @brief 根据设备商ID和设备ID，在拓扑中寻找一个设备
- *
- * @param vendorId
- * @param deviceId
- * @return struct pci_device*
- */
-struct pci_device*
-pci_get_device_by_id(u16_t vendorId, u16_t deviceId);
+bool
+pci_register_driver(struct device_def* def, pci_id_checker_t checker);
 
 /**
  * @brief 初始化PCI设备的基地址寄存器。返回由该基地址代表的，
@@ -151,33 +114,116 @@ pci_get_device_by_id(u16_t vendorId, u16_t deviceId);
  * @return size_t
  */
 size_t
-pci_bar_sizing(struct pci_device* dev, u32_t* bar_out, u32_t bar_num);
+pci_bar_sizing(struct pci_probe* probe, u32_t* bar_out, u32_t bar_num);
+
+irq_t
+pci_declare_msi_irq(irq_servant callback, struct pci_probe* probe);
+
+int
+pci_assign_msi(struct pci_probe* probe, irq_t irq, void* irq_spec);
 
 /**
- * @brief 配置并启用设备MSI支持。
- * 参阅：PCI LB Spec. (Rev 3) Section 6.8 & 6.8.1
- * 以及：Intel Manual, Vol 3, Section 10.11
+ * @brief Bind an abstract device instance to the pci device
  *
- * @param device PCI device
- * @param vector interrupt vector.
+ * @param pcidev pci device
+ * @param dev abstract device instance
  */
-void
-pci_setup_msi(struct pci_device* device, int vector);
+static inline void
+pci_bind_instance(struct pci_probe* probe, struct device* dev)
+{
+    probe->bind = dev;
 
-void
-pci_add_driver(const char* name,
-               u32_t class,
-               u32_t vendor,
-               u32_t devid,
-               pci_drv_init init);
+}
 
 int
-pci_bind_driver(struct pci_device* pci_dev);
+pci_bind_driver(struct pci_registry* reg);
+
+
+static inline unsigned int
+pci_device_vendor(struct pci_probe* probe)
+{
+    return PCI_DEV_VENDOR(probe->device_info);
+}
+
+static inline unsigned int
+pci_device_devid(struct pci_probe* probe)
+{
+    return PCI_DEV_DEVID(probe->device_info);
+}
+
+static inline unsigned int
+pci_device_class(struct pci_probe* probe)
+{
+    return PCI_DEV_CLASS(probe->class_info);
+}
+
+static inline struct pci_base_addr*
+pci_device_bar(struct pci_probe* probe, int index)
+{
+    return &probe->bar[index];
+}
+
+static inline void
+pci_cmd_set_mmio(pci_reg_t* cmd)
+{
+    *cmd |= PCI_RCMD_MM_ACCESS;
+}
+
+static inline ptr_t
+pci_requester_id(struct pci_probe* probe)
+{
+    return probe->loc;
+}
+
+static inline void
+pci_cmd_set_pmio(pci_reg_t* cmd)
+{
+    *cmd |= PCI_RCMD_IO_ACCESS;
+}
+
+static inline void
+pci_cmd_set_msi(pci_reg_t* cmd)
+{
+    *cmd |= PCI_RCMD_DISABLE_INTR;
+}
+
+static inline void
+pci_cmd_set_bus_master(pci_reg_t* cmd)
+{
+    *cmd |= PCI_RCMD_BUS_MASTER;
+}
+
+static inline void
+pci_cmd_set_fast_b2b(pci_reg_t* cmd)
+{
+    *cmd |= PCI_RCMD_FAST_B2B;
+}
+
+static inline bool
+pci_bar_mmio_space(struct pci_base_addr* bar)
+{
+    return (bar->type & BAR_TYPE_MMIO);
+}
+
+static inline bool
+pci_capability_msi(struct pci_probe* probe)
+{
+    return !!probe->msi_loc;
+}
+
+static inline int
+pci_intr_irq(struct pci_probe* probe)
+{
+    return PCI_INTR_IRQ(probe->intr_info);
+}
 
 void
-pci_probe_bar_info(struct pci_device* device);
+pci_apply_command(struct pci_probe* probe, pci_reg_t cmd);
+
+pci_reg_t
+pci_read_cspace(ptr_t base, int offset);
 
 void
-pci_probe_msi_info(struct pci_device* device);
+pci_write_cspace(ptr_t base, int offset, pci_reg_t data);
 
 #endif /* __LUNAIX_PCI_H */