X-Git-Url: https://scm.lunaixsky.com/lunaix-os.git/blobdiff_plain/839da03f6ebe838d780e52190318d4c3048990f1..290981180b9abc454e017271a8ebe75478c00e86:/lunaix-os/includes/hal/pci.h

diff --git a/lunaix-os/includes/hal/pci.h b/lunaix-os/includes/hal/pci.h
index b31352b..95d5fb8 100644
--- a/lunaix-os/includes/hal/pci.h
+++ b/lunaix-os/includes/hal/pci.h
@@ -34,7 +34,12 @@
 #define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)
 
 #define PCI_MSI_ADDR(msi_base) ((msi_base) + 4)
-#define PCI_MSI_DATA(msi_base) ((msi_base) + 8)
+#define PCI_MSI_DATA(msi_base, offset) ((msi_base) + 8 + offset)
+#define PCI_MSI_MASK(msi_base, offset) ((msi_base) + 0xc + offset)
+
+#define MSI_CAP_64BIT 0x80
+#define MSI_CAP_MASK 0x100
+#define MSI_CAP_ENABLE 0x1
 
 #define PCI_RCMD_DISABLE_INTR (1 << 10)
 #define PCI_RCMD_FAST_B2B (1 << 9)
@@ -51,6 +56,16 @@ typedef unsigned int pci_reg_t;
 // PCI device header format
 // Ref: "PCI Local Bus Specification, Rev.3, Section 6.1"
 
+#define BAR_TYPE_MMIO 0x1
+#define BAR_TYPE_CACHABLE 0x2
+
+struct pci_base_addr
+{
+    uint32_t start;
+    uint32_t size;
+    uint32_t type;
+};
+
 struct pci_device
 {
     struct llist_header dev_chain;
@@ -59,19 +74,20 @@ struct pci_device
     uint32_t cspace_base;
     uint32_t msi_loc;
     uint16_t intr_info;
+    struct pci_base_addr bar[6];
 };
 
 // PCI Configuration Space (C-Space) r/w:
 //      Refer to "PCI Local Bus Specification, Rev.3, Section 3.2.2.3.2"
 
-inline pci_reg_t
+static inline pci_reg_t
 pci_read_cspace(uint32_t base, int offset)
 {
     io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
     return io_inl(PCI_CONFIG_DATA);
 }
 
-inline void
+static inline void
 pci_write_cspace(uint32_t base, int offset, pci_reg_t data)
 {
     io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
@@ -86,9 +102,6 @@ pci_write_cspace(uint32_t base, int offset, pci_reg_t data)
 void
 pci_init();
 
-void
-pci_print_device();
-
 /**
  * @brief 根据类型代码（Class Code）去在拓扑中寻找一个设备
  * 类型代码请参阅： PCI LB Spec. Appendix D.