X-Git-Url: https://scm.lunaixsky.com/lunaix-os.git/blobdiff_plain/9fe5e02cf615ad121c4460fbaaac2787d1e09c0e..0eabc11fcf240415e39f3873dfce7cd9384b3042:/lunaix-os/hal/cpu.c

diff --git a/lunaix-os/hal/cpu.c b/lunaix-os/hal/cpu.c
index ad1b0a5..b8a5e9b 100644
--- a/lunaix-os/hal/cpu.c
+++ b/lunaix-os/hal/cpu.c
@@ -1,11 +1,14 @@
+#include <cpuid.h>
 #include <hal/cpu.h>
+#include <hal/rnd.h>
 #include <stdint.h>
-#include <cpuid.h>
 
-void cpu_get_model(char* model_out) {
-    uint32_t* out = (uint32_t*)model_out;
+void
+cpu_get_model(char* model_out)
+{
+    u32_t* out = (u32_t*)model_out;
     reg32 eax = 0, ebx = 0, edx = 0, ecx = 0;
-    
+
     __get_cpuid(0, &eax, &ebx, &ecx, &edx);
 
     out[0] = ebx;
@@ -16,26 +19,63 @@ void cpu_get_model(char* model_out) {
 
 #define BRAND_LEAF 0x80000000UL
 
-int cpu_brand_string_supported() {
+int
+cpu_brand_string_supported()
+{
     reg32 supported = __get_cpuid_max(BRAND_LEAF, 0);
     return (supported >= 0x80000004UL);
 }
 
-void cpu_get_brand(char* brand_out) {
-    if(!cpu_brand_string_supported()) {
+void
+cpu_get_brand(char* brand_out)
+{
+    if (!cpu_brand_string_supported()) {
         brand_out[0] = '?';
         brand_out[1] = '\0';
     }
-    uint32_t* out = (uint32_t*) brand_out;
+    u32_t* out = (u32_t*)brand_out;
     reg32 eax = 0, ebx = 0, edx = 0, ecx = 0;
-    for (uint32_t i = 2, j = 0; i < 5; i++)
-    {
+    for (u32_t i = 2, j = 0; i < 5; i++) {
         __get_cpuid(BRAND_LEAF + i, &eax, &ebx, &ecx, &edx);
         out[j] = eax;
         out[j + 1] = ebx;
         out[j + 2] = ecx;
         out[j + 3] = edx;
-        j+=4;
+        j += 4;
     }
     brand_out[48] = '\0';
+}
+
+int
+cpu_has_apic()
+{
+    // reference: Intel manual, section 10.4.2
+    reg32 eax = 0, ebx = 0, edx = 0, ecx = 0;
+    __get_cpuid(1, &eax, &ebx, &ecx, &edx);
+
+    return (edx & 0x100);
+}
+
+void
+cpu_rdmsr(u32_t msr_idx, u32_t* reg_high, u32_t* reg_low)
+{
+    u32_t h = 0, l = 0;
+    asm volatile("rdmsr" : "=d"(h), "=a"(l) : "c"(msr_idx));
+
+    *reg_high = h;
+    *reg_low = l;
+}
+
+void
+cpu_wrmsr(u32_t msr_idx, u32_t reg_high, u32_t reg_low)
+{
+    asm volatile("wrmsr" : : "d"(reg_high), "a"(reg_low), "c"(msr_idx));
+}
+
+int
+rnd_is_supported()
+{
+    reg32 eax, ebx, ecx, edx;
+    __get_cpuid(0x01, &eax, &ebx, &ecx, &edx);
+    return (ecx & (1 << 30));
 }
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