X-Git-Url: https://scm.lunaixsky.com/lunaix-os.git/blobdiff_plain/9fe5e02cf615ad121c4460fbaaac2787d1e09c0e..6195e9739894771c56ea9bd3cba7bd7d04d8e7bc:/lunaix-os/includes/hal/ahci.h

diff --git a/lunaix-os/includes/hal/ahci.h b/lunaix-os/includes/hal/ahci.h
index fc457eb..dc30ca8 100644
--- a/lunaix-os/includes/hal/ahci.h
+++ b/lunaix-os/includes/hal/ahci.h
@@ -1,5 +1,80 @@
 #ifndef __LUNAIX_AHCI_H
 #define __LUNAIX_AHCI_H
-// TODO: AHCI Drivers
+
+/*
+ * Macro naming rule:
+ *      HBA_R[xxx]
+ *          HBA Register [xxx]
+ *          e.g. HBA_RPxCLB is Register PxCLB
+ *
+ * All registers offset are 0 based index of a DWORD array
+ */
+
+#define AHCI_HBA_CLASS 0x10601
+
+#define HBA_RCAP 0
+#define HBA_RGHC 1
+#define HBA_RIS 2
+#define HBA_RPI 3
+#define HBA_RVER 4
+
+#define HBA_RPBASE (0x40)
+#define HBA_RPSIZE (0x80 >> 2)
+#define HBA_RPxCLB 0
+#define HBA_RPxFB 2
+#define HBA_RPxIS 4
+#define HBA_RPxIE 5
+#define HBA_RPxCMD 6
+#define HBA_RPxTFD 8
+#define HBA_RPxSIG 9
+#define HBA_RPxSSTS 10
+#define HBA_RPxSCTL 11
+#define HBA_RPxSERR 12
+#define HBA_RPxSACT 13
+#define HBA_RPxCI 14
+#define HBA_RPxSNTF 15
+#define HBA_RPxFBS 16
+
+#define HBA_PxCMD_FRE (1 << 4)
+#define HBA_PxCMD_ST (1)
+#define HBA_PxINTR_DMA (1 << 2)
+#define HBA_PxINTR_D2HR (1)
+
+#define HBA_RGHC_ACHI_ENABLE (1 << 31)
+#define HBA_RGHC_INTR_ENABLE (1 << 1)
+#define HBA_RGHC_RESET 1
+
+#define HBA_RPxSSTS_PWR(x) (((x) >> 8) & 0xf)
+#define HBA_RPxSSTS_IF(x) (((x) >> 4) & 0xf)
+#define HBA_RPxSSTS_PHYSTATE(x) ((x)&0xf)
+
+typedef unsigned int hba_reg_t;
+
+struct ahci_port
+{
+    hba_reg_t* regs;
+    unsigned int ssts;
+    void* cmdlstv;
+    void* fisv;
+};
+
+struct ahci_hba
+{
+    volatile hba_reg_t* base;
+    unsigned int ports_num;
+    unsigned int cmd_slots;
+    unsigned int version;
+    struct ahci_port* ports[32];
+};
+
+/**
+ * @brief 初始化AHCI与HBA
+ *
+ */
+void
+ahci_init();
+
+void
+ahci_list_device();
 
 #endif /* __LUNAIX_AHCI_H */