X-Git-Url: https://scm.lunaixsky.com/lunaix-os.git/blobdiff_plain/a362b4b2c4abbf2da6ec14cb44a8685a81107f6a..8b8f49b713d64065775fe538232f8639083601bd:/lunaix-os/includes/hal/pci.h

diff --git a/lunaix-os/includes/hal/pci.h b/lunaix-os/includes/hal/pci.h
index 56ca3df..3131aba 100644
--- a/lunaix-os/includes/hal/pci.h
+++ b/lunaix-os/includes/hal/pci.h
@@ -1,13 +1,11 @@
 #ifndef __LUNAIX_PCI_H
 #define __LUNAIX_PCI_H
 
-#include <hal/io.h>
+#include <lunaix/device.h>
+#include <lunaix/ds/ldga.h>
 #include <lunaix/ds/llist.h>
 #include <lunaix/types.h>
 
-#define PCI_CONFIG_ADDR 0xcf8
-#define PCI_CONFIG_DATA 0xcfc
-
 #define PCI_TDEV 0x0
 #define PCI_TPCIBRIDGE 0x1
 #define PCI_TCARDBRIDGE 0x2
@@ -18,19 +16,19 @@
 #define PCI_REG_STATUS_CMD 0x4
 #define PCI_REG_BAR(num) (0x10 + (num - 1) * 4)
 
-#define PCI_DEV_VENDOR(x) ((x)&0xffff)
-#define PCI_DEV_DEVID(x) ((x) >> 16)
-#define PCI_INTR_IRQ(x) ((x)&0xff)
-#define PCI_INTR_PIN(x) (((x)&0xff00) >> 8)
+#define PCI_DEV_VENDOR(x) ((x) & 0xffff)
+#define PCI_DEV_DEVID(x) (((x) & 0xffff0000) >> 16)
+#define PCI_INTR_IRQ(x) ((x) & 0xff)
+#define PCI_INTR_PIN(x) (((x) & 0xff00) >> 8)
 #define PCI_DEV_CLASS(x) ((x) >> 8)
-#define PCI_DEV_REV(x) (((x)&0xff))
+#define PCI_DEV_REV(x) (((x) & 0xff))
 #define PCI_BUS_NUM(x) (((x) >> 16) & 0xff)
 #define PCI_SLOT_NUM(x) (((x) >> 11) & 0x1f)
 #define PCI_FUNCT_NUM(x) (((x) >> 8) & 0x7)
 
-#define PCI_BAR_MMIO(x) (!((x)&0x1))
-#define PCI_BAR_CACHEABLE(x) ((x)&0x8)
-#define PCI_BAR_TYPE(x) ((x)&0x6)
+#define PCI_BAR_MMIO(x) (!((x) & 0x1))
+#define PCI_BAR_CACHEABLE(x) ((x) & 0x8)
+#define PCI_BAR_TYPE(x) ((x) & 0x6)
 #define PCI_BAR_ADDR_MM(x) ((x) & ~0xf)
 #define PCI_BAR_ADDR_IO(x) ((x) & ~0x3)
 
@@ -49,8 +47,10 @@
 #define PCI_RCMD_IO_ACCESS 1
 
 #define PCI_ADDRESS(bus, dev, funct)                                           \
-    (((bus)&0xff) << 16) | (((dev)&0xff) << 11) | (((funct)&0xff) << 8) |      \
-      0x80000000
+    (((bus) & 0xff) << 16) | (((dev) & 0xff) << 11) |                          \
+      (((funct) & 0xff) << 8) | 0x80000000
+
+#define PCI_ID_ANY (-1)
 
 typedef unsigned int pci_reg_t;
 
@@ -61,8 +61,6 @@ typedef unsigned int pci_reg_t;
 #define BAR_TYPE_CACHABLE 0x2
 #define PCI_DRV_NAME_LEN 32
 
-struct pci_driver;
-
 struct pci_base_addr
 {
     u32_t start;
@@ -72,56 +70,30 @@ struct pci_base_addr
 
 struct pci_device
 {
+    struct device dev;
     struct llist_header dev_chain;
     u32_t device_info;
     u32_t class_info;
     u32_t cspace_base;
     u32_t msi_loc;
-    uint16_t intr_info;
-    struct
-    {
-        struct pci_driver* type;
-        void* instance;
-    } driver;
+    u16_t intr_info;
     struct pci_base_addr bar[6];
 };
+#define PCI_DEVICE(devbase) (container_of((devbase), struct pci_device, dev))
 
 typedef void* (*pci_drv_init)(struct pci_device*);
 
-struct pci_driver
+#define PCI_DEVIDENT(vendor, id)                                               \
+    ((((id) & 0xffff) << 16) | (((vendor) & 0xffff)))
+
+struct pci_device_def
 {
-    struct llist_header drivers;
-    u32_t dev_info;
     u32_t dev_class;
-    pci_drv_init create_driver;
-    char name[PCI_DRV_NAME_LEN];
+    u32_t dev_ident;
+    u32_t ident_mask;
+    struct device_def devdef;
 };
 
-// PCI Configuration Space (C-Space) r/w:
-//      Refer to "PCI Local Bus Specification, Rev.3, Section 3.2.2.3.2"
-
-static inline pci_reg_t
-pci_read_cspace(u32_t base, int offset)
-{
-    io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
-    return io_inl(PCI_CONFIG_DATA);
-}
-
-static inline void
-pci_write_cspace(u32_t base, int offset, pci_reg_t data)
-{
-    io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
-    io_outl(PCI_CONFIG_DATA, data);
-}
-
-/**
- * @brief 初始化PCI。这主要是通过扫描PCI总线进行拓扑重建。注意，该
- * 初始化不包括针对每个设备的初始化，因为那是设备驱动的事情。
- *
- */
-void
-pci_init();
-
 /**
  * @brief 根据类型代码（Class Code）去在拓扑中寻找一个设备
  * 类型代码请参阅： PCI LB Spec. Appendix D.
@@ -138,7 +110,7 @@ struct pci_device* pci_get_device_by_class(u32_t class);
  * @return struct pci_device*
  */
 struct pci_device*
-pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId);
+pci_get_device_by_id(u16_t vendorId, u16_t deviceId);
 
 /**
  * @brief 初始化PCI设备的基地址寄存器。返回由该基地址代表的，
@@ -153,17 +125,6 @@ pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId);
 size_t
 pci_bar_sizing(struct pci_device* dev, u32_t* bar_out, u32_t bar_num);
 
-/**
- * @brief 配置并启用设备MSI支持。
- * 参阅：PCI LB Spec. (Rev 3) Section 6.8 & 6.8.1
- * 以及：Intel Manual, Vol 3, Section 10.11
- *
- * @param device PCI device
- * @param vector interrupt vector.
- */
-void
-pci_setup_msi(struct pci_device* device, int vector);
-
 void
 pci_add_driver(const char* name,
                u32_t class,
@@ -174,4 +135,10 @@ pci_add_driver(const char* name,
 int
 pci_bind_driver(struct pci_device* pci_dev);
 
+void
+pci_probe_bar_info(struct pci_device* device);
+
+void
+pci_probe_msi_info(struct pci_device* device);
+
 #endif /* __LUNAIX_PCI_H */