X-Git-Url: https://scm.lunaixsky.com/lunaix-os.git/blobdiff_plain/a8b800d1691263aa73054449b1721c1ec9516496..d1b1c8d9119229dbeed06cd252917e54a1cb77f6:/lunaix-os/includes/hal/pci.h diff --git a/lunaix-os/includes/hal/pci.h b/lunaix-os/includes/hal/pci.h index 8c18997..da45090 100644 --- a/lunaix-os/includes/hal/pci.h +++ b/lunaix-os/includes/hal/pci.h @@ -6,8 +6,8 @@ #include #include -#define EXPORT_PCI_DEVICE(id, pci_devdef) \ - EXPORT_DEVICE(id, &(pci_devdef)->devdef, load_pci_probe) +#define EXPORT_PCI_DEVICE(id, pci_devdef, stage) \ + EXPORT_DEVICE(id, &(pci_devdef)->devdef, stage) #define PCI_MATCH_EXACT -1 #define PCI_MATCH_ANY 0 @@ -39,7 +39,8 @@ #define PCI_BAR_ADDR_MM(x) ((x) & ~0xf) #define PCI_BAR_ADDR_IO(x) ((x) & ~0x3) -#define PCI_MSI_ADDR(msi_base) ((msi_base) + 4) +#define PCI_MSI_ADDR_LO(msi_base) ((msi_base) + 4) +#define PCI_MSI_ADDR_HI(msi_base) ((msi_base) + 8) #define PCI_MSI_DATA(msi_base, offset) ((msi_base) + 8 + offset) #define PCI_MSI_MASK(msi_base, offset) ((msi_base) + 0xc + offset) @@ -53,13 +54,18 @@ #define PCI_RCMD_MM_ACCESS (1 << 1) #define PCI_RCMD_IO_ACCESS 1 -#define PCI_ADDRESS(bus, dev, funct) \ - (((bus) & 0xff) << 16) | (((dev) & 0xff) << 11) | \ - (((funct) & 0xff) << 8) | 0x80000000 +#define PCI_CFGADDR(pciloc) ((u32_t)(pciloc) << 8) | 0x80000000UL + +#define PCILOC(bus, dev, funct) \ + (((bus) & 0xff) << 8) | (((dev) & 0x1f) << 3) | ((funct) & 0x7) +#define PCILOC_BUS(loc) (((loc) >> 8) & 0xff) +#define PCILOC_DEV(loc) (((loc) >> 3) & 0x1f) +#define PCILOC_FN(loc) ((loc) & 0x7) #define PCI_ID_ANY (-1) typedef unsigned int pci_reg_t; +typedef u16_t pciaddr_t; // PCI device header format // Ref: "PCI Local Bus Specification, Rev.3, Section 6.1" @@ -79,15 +85,30 @@ struct pci_device { struct device dev; struct llist_header dev_chain; + struct hlist_node dev_cache; + + struct + { + struct device* dev; + struct device_def* def; + } binding; + + pciaddr_t loc; + u16_t intr_info; u32_t device_info; u32_t class_info; u32_t cspace_base; u32_t msi_loc; - u16_t intr_info; struct pci_base_addr bar[6]; }; #define PCI_DEVICE(devbase) (container_of((devbase), struct pci_device, dev)) +struct pci_device_list +{ + struct llist_header peers; + struct pci_device* pcidev; +}; + typedef void* (*pci_drv_init)(struct pci_device*); #define PCI_DEVIDENT(vendor, id) \ @@ -100,6 +121,10 @@ struct pci_device_def u32_t ident_mask; struct device_def devdef; }; +#define pcidev_def(dev_def_ptr) \ + container_of((dev_def_ptr), struct pci_device_def, devdef) + +#define binded_pcidev(pcidev) ((pcidev)->binding.def) /** * @brief 根据类型代码(Class Code)去在拓扑中寻找一个设备 @@ -132,20 +157,28 @@ pci_get_device_by_id(u16_t vendorId, u16_t deviceId); size_t pci_bar_sizing(struct pci_device* dev, u32_t* bar_out, u32_t bar_num); +/** + * @brief Bind an abstract device instance to the pci device + * + * @param pcidev pci device + * @param devobj abstract device instance + */ void -pci_add_driver(const char* name, - u32_t class, - u32_t vendor, - u32_t devid, - pci_drv_init init); - -int -pci_bind_driver(struct pci_device* pci_dev); +pci_bind_instance(struct pci_device* pcidev, void* devobj); void pci_probe_bar_info(struct pci_device* device); +void +pci_setup_msi(struct pci_device* device, int vector); + void pci_probe_msi_info(struct pci_device* device); +int +pci_bind_definition(struct pci_device_def* pcidev_def, int* more); + +int +pci_bind_definition_all(struct pci_device_def* pcidef); + #endif /* __LUNAIX_PCI_H */