X-Git-Url: https://scm.lunaixsky.com/lunaix-os.git/blobdiff_plain/c1811aecaae88bc006ce20bd301a6519dd89abda..eb1d71eb06e977f9ea61f6f43e5ce65342faf1cc:/lunaix-os/hal/cpu.c?ds=sidebyside

diff --git a/lunaix-os/hal/cpu.c b/lunaix-os/hal/cpu.c
index d57ae26..ab5432c 100644
--- a/lunaix-os/hal/cpu.c
+++ b/lunaix-os/hal/cpu.c
@@ -40,40 +40,28 @@ void cpu_get_brand(char* brand_out) {
     brand_out[48] = '\0';
 }
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wreturn-type"
-reg32 cpu_r_cr0() {
-    asm volatile ("mov %cr0, %eax");
-}
-
-reg32 cpu_r_cr2() {
-    asm volatile ("mov %cr2, %eax");
-}
-
-reg32 cpu_r_cr3() {
-    asm volatile ("mov %cr3, %eax");
-}
-#pragma GCC diagnostic push
 
-void cpu_w_cr0(reg32 v) {
-    asm volatile (
-        "mov %0, %%cr0"
-        :: "r"(v)
-    );
+int
+cpu_has_apic() {
+    // reference: Intel manual, section 10.4.2
+    reg32 eax = 0, ebx = 0, edx = 0, ecx = 0;
+    __get_cpuid(1, &eax, &ebx, &ecx, &edx);
+    
+    return (edx & 0x100);
 }
 
-void cpu_w_cr2(reg32 v) {
-    asm volatile (
-        "mov %0, %%cr2"
-        :: "r"(v)
-    );
-}
+void
+cpu_rdmsr(uint32_t msr_idx, uint32_t* reg_high, uint32_t* reg_low)
+{
+    uint32_t h = 0, l = 0;
+    asm volatile("rdmsr" : "=d"(h), "=a"(l) : "c"(msr_idx));
 
-void cpu_w_cr3(reg32 v) {
-    asm volatile (
-        "mov %0, %%cr3"
-        :: "r"(v)
-    );
+    *reg_high = h;
+    *reg_low = l;
 }
 
-
+void
+cpu_wrmsr(uint32_t msr_idx, uint32_t reg_high, uint32_t reg_low)
+{
+    asm volatile("wrmsr" : : "d"(reg_high), "a"(reg_low), "c"(msr_idx));
+}
\ No newline at end of file