X-Git-Url: https://scm.lunaixsky.com/lunaix-os.git/blobdiff_plain/ca92c307e7d125e56311cce13d5d0b1b00694238..0e1309c02f0703c050df09b71346dab60fc6df87:/lunaix-os/hal/pci.c

diff --git a/lunaix-os/hal/pci.c b/lunaix-os/hal/pci.c
index dd4e95b..d626768 100644
--- a/lunaix-os/hal/pci.c
+++ b/lunaix-os/hal/pci.c
@@ -1,6 +1,18 @@
+/**
+ * @file pci.c
+ * @author Lunaixsky (zelong56@gmail.com)
+ * @brief A software implementation of PCI Local Bus Specification Revision 3.0
+ * @version 0.1
+ * @date 2022-06-28
+ *
+ * @copyright Copyright (c) 2022
+ *
+ */
+#include <hal/acpi/acpi.h>
 #include <hal/apic.h>
 #include <hal/pci.h>
-#include <lunaix/mm/kalloc.h>
+#include <lunaix/mm/valloc.h>
+#include <lunaix/spike.h>
 #include <lunaix/syslog.h>
 
 LOG_MODULE("PCI")
@@ -24,7 +36,10 @@ pci_probe_device(int bus, int dev, int funct)
     pci_reg_t hdr_type = pci_read_cspace(base, 0xc);
     hdr_type = (hdr_type >> 16) & 0xff;
 
-    if ((hdr_type & 0x80)) {
+    // 防止堆栈溢出
+    // QEMU的ICH9/Q35实现似乎有点问题，对于多功能设备的每一个功能的header type
+    //  都将第七位置位。而virtualbox 就没有这个毛病。
+    if ((hdr_type & 0x80) && funct == 0) {
         hdr_type = hdr_type & ~0x80;
         // 探测多用途设备（multi-function device）
         for (int i = 1; i < 7; i++) {
@@ -40,7 +55,7 @@ pci_probe_device(int bus, int dev, int funct)
     pci_reg_t intr = pci_read_cspace(base, 0x3c);
     pci_reg_t class = pci_read_cspace(base, 0x8);
 
-    struct pci_device* device = lxmalloc(sizeof(struct pci_device));
+    struct pci_device* device = valloc(sizeof(struct pci_device));
     *device = (struct pci_device){ .cspace_base = base,
                                    .class_info = class,
                                    .device_info = reg1,
@@ -66,6 +81,9 @@ pci_probe()
 void
 pci_probe_msi_info(struct pci_device* device)
 {
+    // Note that Virtualbox have to use ICH9 chipset for MSI support.
+    // Qemu seems ok with default PIIX3, Bochs is pending to test...
+    //    See https://www.virtualbox.org/manual/ch03.html (section 3.5.1)
     pci_reg_t status =
       pci_read_cspace(device->cspace_base, PCI_REG_STATUS_CMD) >> 16;
 
@@ -148,6 +166,7 @@ pci_bar_sizing(struct pci_device* dev, uint32_t* bar_out, uint32_t bar_num)
         sized = PCI_BAR_ADDR_MM(sized);
     }
     *bar_out = bar;
+    pci_write_cspace(dev->cspace_base, PCI_REG_BAR(bar_num), bar);
     return ~sized + 1;
 }
 
@@ -155,20 +174,29 @@ void
 pci_setup_msi(struct pci_device* device, int vector)
 {
     // Dest: APIC#0, Physical Destination, No redirection
-    uint32_t msi_addr = (__APIC_BASE_PADDR | 0x8);
+    uint32_t msi_addr = (__APIC_BASE_PADDR);
 
     // Edge trigger, Fixed delivery
     uint32_t msi_data = vector;
 
     pci_write_cspace(
       device->cspace_base, PCI_MSI_ADDR(device->msi_loc), msi_addr);
-    pci_write_cspace(
-      device->cspace_base, PCI_MSI_DATA(device->msi_loc), msi_data & 0xffff);
 
     pci_reg_t reg1 = pci_read_cspace(device->cspace_base, device->msi_loc);
+    pci_reg_t msg_ctl = reg1 >> 16;
+
+    int offset = !!(msg_ctl & MSI_CAP_64BIT) * 4;
+    pci_write_cspace(device->cspace_base,
+                     PCI_MSI_DATA(device->msi_loc, offset),
+                     msi_data & 0xffff);
+
+    if ((msg_ctl & MSI_CAP_MASK)) {
+        pci_write_cspace(
+          device->cspace_base, PCI_MSI_MASK(device->msi_loc, offset), 0);
+    }
 
     // manipulate the MSI_CTRL to allow device using MSI to request service.
-    reg1 = ((((reg1 >> 16) & ~0x70) | 0x1) << 16) | (reg1 & 0xffff);
+    reg1 = (reg1 & 0xff8fffff) | 0x10000;
     pci_write_cspace(device->cspace_base, device->msi_loc, reg1);
 }
 
@@ -205,5 +233,12 @@ void
 pci_init()
 {
     llist_init_head(&pci_devices);
+    acpi_context* acpi = acpi_get_context();
+    assert_msg(acpi, "ACPI not initialized.");
+    if (acpi->mcfg.alloc_num) {
+        // PCIe Enhanced Configuration Mechanism is supported.
+        // TODO: support PCIe addressing mechanism
+    }
+    // Otherwise, fallback to use legacy PCI 3.0 method.
     pci_probe();
 }
\ No newline at end of file