X-Git-Url: https://scm.lunaixsky.com/lunaix-os.git/blobdiff_plain/ebb55b7e5f0b8f31328950ec383b77b208ffbb64..378a473943ba2bfe38c303d198aab41056095b71:/lunaix-os/hal/char/uart/16x50_base.c diff --git a/lunaix-os/hal/char/uart/16x50_base.c b/lunaix-os/hal/char/uart/16x50_base.c index 6e94b84..5b14445 100644 --- a/lunaix-os/hal/char/uart/16x50_base.c +++ b/lunaix-os/hal/char/uart/16x50_base.c @@ -16,6 +16,7 @@ uart_alloc(ptr_t base_addr) uart->cntl_save.rie = 0; uart->base_addr = base_addr; + uart->base_clk = 115200U; return uart; } @@ -69,9 +70,29 @@ uart_general_exec_cmd(struct serial_dev* sdev, u32_t req, va_list args) case SERIO_RXDA: uart_clrie(uart); break; - case SERIO_SETBRDIV: - // TODO - break; + case SERIO_SETBRDRATE: + { + unsigned int div, rate; + + rate = va_arg(args, speed_t); + if (!rate) { + return EINVAL; + } + + div = uart->base_clk / va_arg(args, speed_t); + uart_baud_divisor(uart, div); + break; + } + case SERIO_SETBRDBASE: + { + int clk = va_arg(args, unsigned int); + if (!clk) { + return EINVAL; + } + + uart->base_clk = clk; + break; + } case SERIO_SETCNTRLMODE: uart_set_control_mode(uart, va_arg(args, tcflag_t)); break; @@ -82,13 +103,13 @@ uart_general_exec_cmd(struct serial_dev* sdev, u32_t req, va_list args) } void -uart_handle_irq_overlap(int iv, struct llist_header* ports) +uart_handle_irq_overlap(irq_t irq, struct llist_header* ports) { struct uart16550 *pos, *n; llist_for_each(pos, n, ports, local_ports) { int is = uart_intr_identify(pos); - if (iv == pos->iv && (is == UART_CHR_TIMEOUT)) { + if (irq == pos->irq && (is == UART_CHR_TIMEOUT)) { goto done; } } @@ -96,11 +117,11 @@ uart_handle_irq_overlap(int iv, struct llist_header* ports) return; done: - uart_handle_irq(iv, pos); + uart_handle_irq(irq, pos); } void -uart_handle_irq(int iv, struct uart16550 *uart) +uart_handle_irq(irq_t irq, struct uart16550 *uart) { char tmpbuf[32]; char recv;