Unifying the Lunaix's Physical Memory Model (#28)

* * Introduce new physical page model, which swap out the previous
  address based one, also support dynamically allocate required
  page list based on system mem map provided by upstream bootloader

* Rename page alignment utils from pagetable.h for better expresivenness

* Rewrite the next fit allocator with order-based free-list caching
  feature. (PMALLOC_SIMPLE)

* Intented to add more advanced pmem allocator.

* Add config.h file that provide finer control on the "hyperparameter"
  of Lunaix kernel (we should switch to tools like kconfig later)

* * Introduce struct leaflet, which is a wrapper around struct ppage
  used to tackle the ambiguity of head or tail when struct ppage
  has a order > 0 base page compounded.

* Refactoring done regarding to this new abstraction.

* * Fix compiler-time errors

* Remove the pmm_init_freeze_range api and init_begin/end things
  this forcing allocator to explicitly initialize entire pplist
  during a single pmm_init invoke

* Address all issues found when doing smoking through bootstraping
  stage

* * Fix issues discovered when preforming smoke test from bootstage to
  initd spawn.

     1. pte skipped from copying for grouped pages.
     2. symlink creation ignore the null terminator in ramfs
     3. Add null-ptr termination on when user-provided envp
        and argc are absent (thus only default one get injected)
     4. physical page does not get marked as initialized when
        allocated from uninitialized memory region
     5. a typo cause vunmap accidentially remove L0T mapping
     6. ahci: fis and cb region should not mapped through ioremap.

* Need investigate: seems the physical page got smashed with each
  other when intensive alloc and freeing taking place. Could be
  issues within allocator

* * Fix issue that dup_leaflet copy incomplete data when dealing with
  leaflet with order > 1. This due to lack of flush ranged tlb records

* Fix a memory leakage on leaflet when releasing thread kstack

* * Rework the tlb flushing functions, introduce the ability to respect
  different address space, this allow seamless porting to architecture
  with TLB ASID-tagging support to eliminate un-needed tlb flushing

* * Remove obsoleted vmm api

* * Move all kernel built-in stack to dedicated section

* Add failsafe stack to run failsafe handler without need to worry
  current stack validity (as everything could be messed up when
  shit happened)

* Add failsafe handler to gather diagnostic info and centralise
  stack trace printing, which is robost as it use an dedicated
  stack and all calling being inlined so avoid any stack operation
  before entering it

* Add check on init stack smashing.

* * (LunaDBG) update pmem profiling to reflect the latest changes