From: Minep Date: Thu, 5 Sep 2024 23:01:18 +0000 (+0100) Subject: layout boot-stage framework for aa64 X-Git-Url: https://scm.lunaixsky.com/lunaix-os.git/commitdiff_plain/e47950ba3c4ef27ff19d8bb7ad54d779180e96e9?ds=sidebyside;hp=-c layout boot-stage framework for aa64 * define system regsiters and it's operations * fix display issue in lunamenu --- e47950ba3c4ef27ff19d8bb7ad54d779180e96e9 diff --git a/lunaix-os/arch/LBuild b/lunaix-os/arch/LBuild index 8617597..7ead995 100644 --- a/lunaix-os/arch/LBuild +++ b/lunaix-os/arch/LBuild @@ -2,7 +2,7 @@ use({ config("arch"): { "i386": "x86", "x86_64": "x86", - "aarch64": "arm", + "aarch64": "aarch64", "rv64": "riscv" } }) \ No newline at end of file diff --git a/lunaix-os/arch/LConfig b/lunaix-os/arch/LConfig index 7afea85..335e67b 100644 --- a/lunaix-os/arch/LConfig +++ b/lunaix-os/arch/LConfig @@ -12,7 +12,7 @@ def architecture_support(): Config ISA support """ # type(["i386", "x86_64", "aarch64", "rv64"]) - type(["i386", "x86_64"]) + type(["i386", "x86_64", "aarch64"]) default("x86_64") env_val = env("ARCH") diff --git a/lunaix-os/arch/aarch64/LBuild b/lunaix-os/arch/aarch64/LBuild new file mode 100644 index 0000000..07bebb0 --- /dev/null +++ b/lunaix-os/arch/aarch64/LBuild @@ -0,0 +1,7 @@ + +compile_opts([ + "-mlittle-endian", + "-mgeneral-regs-only", + "-mabi=lp64", + "-mno-omit-leaf-frame-pointer" +]) \ No newline at end of file diff --git a/lunaix-os/arch/aarch64/boot/init.c b/lunaix-os/arch/aarch64/boot/init.c new file mode 100644 index 0000000..6b72e6e --- /dev/null +++ b/lunaix-os/arch/aarch64/boot/init.c @@ -0,0 +1,99 @@ +#include +#include + +#include "init.h" + +static inline void +setup_pstate() +{ + /* + SCTRL_EL1 + EE=0, E0E=0 // all little endian + WXN=1 // write implie exec never + SA0=1, SA=1 // alignment check on SP + A=1 // alignment check on memref + NMI=1 // mask interrupt + M=1 // enable mmu + */ + + unsigned long sctrl = 0; + + sctrl |= SCTRL_NMI; + sctrl |= SCTRL_WXN | SCTRL_nAA; + sctrl |= SCTRL_SA | SCTRL_SA0; + sctrl |= SCTRL_A | SCTRL_M; + + set_sysreg(TCR_EL1, sctrl); + set_sysreg(SPSel, 1); +} + +static inline void +setup_evbar() +{ + // TODO install exception vectors, setup VBAR +} + +static inline void +setup_ttbr() +{ + /* + + TCR_EL1 + SH0=3 // Inner sharable + ORGN0=0 // Normal memory, Outer Non-cacheable. + IRGN0=1 // Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable. + A1=0 // TTBR0 define ASID + EPD1=0 + T1SZ=0 + EPD0=1 + T0SZ=16 // disable TTBR1, Use TTBR0 for all translation + TG0=0 // VA48, 256T, 4K Granule + TBI1=0, + TBI0=0 // Ignore top bits + AS=1 // 16bits asid + HA=1 + HD=1 // Hardware managed dirty and access + + + We may use the follow practice later + TTBR0: Translation for user-land (lowmem) + TTBR1: Translation for kernel-land (highmem) + */ + + unsigned long tcr = 0; + ptr_t ttb; + + tcr |= TCR_T1SZ(0) | TCR_T0SZ(16); + tcr |= TCR_TG0(TCR_G4K); + tcr |= TCR_AS | TCR_HA | TCR_HD; + tcr |= TCR_EPD0; + + ttb = kremap(); + + set_sysreg(TTBR0_EL1, ttb); + set_sysreg(TCR_EL1, tcr); +} + +static inline void +extract_dtb_bootinfo(ptr_t dtb, struct boot_handoff* handoff) +{ + handoff->kexec.dtb_pa = dtb; + + // TODO extract /memory, /reserved-memories from dtb +} + +struct boot_handoff* +aarch64_init(ptr_t dtb) +{ + setup_evbar(); + setup_ttbr(); + setup_pstate(); + + struct boot_handoff* handoff; + + handoff = bootmem_alloc(sizeof(*handoff)); + + extract_dtb_bootinfo(dtb, handoff); + + return handoff; +} \ No newline at end of file diff --git a/lunaix-os/arch/aarch64/boot/init.h b/lunaix-os/arch/aarch64/boot/init.h new file mode 100644 index 0000000..9668423 --- /dev/null +++ b/lunaix-os/arch/aarch64/boot/init.h @@ -0,0 +1,14 @@ +#ifndef __LUNAIX_AA64_INIT_H +#define __LUNAIX_AA64_INIT_H + +#include +#include + +#define boot_text __attribute__((section(".boot.text"))) +#define boot_data __attribute__((section(".boot.data"))) +#define boot_bss __attribute__((section(".boot.bss"))) + +ptr_t +kremap(); + +#endif /* __LUNAIX_AA64_INIT_H */ diff --git a/lunaix-os/arch/aarch64/boot/kremap.c b/lunaix-os/arch/aarch64/boot/kremap.c new file mode 100644 index 0000000..e69de29 diff --git a/lunaix-os/arch/aarch64/boot/mem.c b/lunaix-os/arch/aarch64/boot/mem.c new file mode 100644 index 0000000..1803e2a --- /dev/null +++ b/lunaix-os/arch/aarch64/boot/mem.c @@ -0,0 +1,32 @@ +#include "init.h" +#include +#include + +#define BOOTMEM_SIZE (4 * 4096) + +static reclaimable char bootmem_pool[BOOTMEM_SIZE]; +static unsigned int pos; + +void* +bootmem_alloc(unsigned int size) +{ + ptr_t res; + + res = __ptr(bootmem_pool) + pos; + + size = ROUNDUP(size, 4); + pos += size; + + if (pos >= BOOTMEM_SIZE) { + spin(); + } + + return (void*)res; +} + +void +bootmem_free(void* ptr) +{ + // not need to support, as they are all one-shot + return; +} \ No newline at end of file diff --git a/lunaix-os/arch/aarch64/boot/start.S b/lunaix-os/arch/aarch64/boot/start.S new file mode 100644 index 0000000..ed11af9 --- /dev/null +++ b/lunaix-os/arch/aarch64/boot/start.S @@ -0,0 +1,26 @@ +.section .boot.data + .align 16 + stack_end: + .skip 512 + stack_top: + +.section .boot.text + .global start_ + + /* + We follow Linux-arm64 boot protocol + ldr x0, dtb + mov x1, xzr + mov x2, xzr + mov x3, xzr + */ + start_: + ldr sp, =stack_top + mov fp, xzr + + ldr x4, =aarch64_init + blx x4 + + // x0: ptr to boot_handoff + ldr x4, =kernel_bootstrap + blx x4 \ No newline at end of file diff --git a/lunaix-os/arch/aarch64/includes/sys/cpu.h b/lunaix-os/arch/aarch64/includes/sys/cpu.h new file mode 100644 index 0000000..8ed9849 --- /dev/null +++ b/lunaix-os/arch/aarch64/includes/sys/cpu.h @@ -0,0 +1,21 @@ +#ifndef __LUNAIX_AA64_CPU_H +#define __LUNAIX_AA64_CPU_H + +#include + +void +cpu_trap_sched(); + +static inline void +cpu_enable_interrupt() +{ + set_sysreg(ALLINT_EL1, 0); +} + +static inline void +cpu_disable_interrupt() +{ + set_sysreg(ALLINT_EL1, 1 << 12); +} + +#endif /* __LUNAIX_AA64_CPU_H */ diff --git a/lunaix-os/arch/aarch64/includes/sys/msrs.h b/lunaix-os/arch/aarch64/includes/sys/msrs.h new file mode 100644 index 0000000..cd8978d --- /dev/null +++ b/lunaix-os/arch/aarch64/includes/sys/msrs.h @@ -0,0 +1,77 @@ +#ifndef __LUNAIX_AA64_MSRS_H +#define __LUNAIX_AA64_MSRS_H + +#include + +#define __sr_encode(op0, op1, crn, crm, op2) \ + s##op0##_##op1##_c##crn##_c##crm##_##op2 + +#define SCTLR_EL1 __sr_encode(3, 0, 1, 0, 0) +#define TCR_EL1 __sr_encode(3, 0, 2, 0, 2) +#define TTBR0_EL1 __sr_encode(3, 0, 2, 0, 0) +#define TTBR1_EL1 __sr_encode(3, 0, 2, 0, 1) +#define VBAR_EL1 __sr_encode(3, 0, 12, 0, 1) +#define CurrentEL __sr_encode(3, 0, 4, 2, 2) +#define ELR_E1 __sr_encode(3, 0, 4, 0, 1) +#define SPSel __sr_encode(3, 0, 4, 2, 0) +#define SPSR_EL1 __sr_encode(3, 0, 4, 0, 0) +#define DAIF_EL1 __sr_encode(3, 3, 4, 2, 1) +#define ALLINT_EL1 __sr_encode(3, 0, 4, 3, 0) +#define SP_EL0 __sr_encode(3, 0, 4, 1, 0) +#define SP_EL1 __sr_encode(3, 4, 4, 1, 0) + +#define read_sysreg(reg) \ + ({ unsigned long _x; \ + asm ("mrs %0, " stringify(reg):"=r"(_x)); \ + _x; \ + }) + +#define set_sysreg(reg, v) \ + ({ unsigned long _x = v; \ + asm ("msr " stringify(reg) ", %0"::"r"(_x)); \ + _x; \ + }) + +#define SCTRL_SPINTMASK (1UL << 62) +#define SCTRL_NMI (1UL << 61) +#define SCTRL_EE (1UL << 25) +#define SCTRL_E0E (1UL << 24) +#define SCTRL_WXN (1UL << 19) +#define SCTRL_nAA (1UL << 6) +#define SCTRL_SA0 (1UL << 4) +#define SCTRL_SA (1UL << 3) +#define SCTRL_A (1UL << 1) +#define SCTRL_M (1UL << 0) + +#define TCR_DS (1UL << 59) +#define TCR_E0PD1 (1UL << 56) +#define TCR_E0PD0 (1UL << 55) +#define TCR_TBID1 (1UL << 52) +#define TCR_TBID0 (1UL << 51) +#define TCR_HPD1 (1UL << 42) +#define TCR_HPD0 (1UL << 41) +#define TCR_HD (1UL << 40) +#define TCR_HA (1UL << 39) +#define TCR_TBI1 (1UL << 38) +#define TCR_TBI0 (1UL << 37) +#define TCR_AS (1UL << 36) + +#define TCR_G4K (0b01) +#define TCR_G16K (0b10) +#define TCR_G64K (0b11) + +#define TCR_SHNS (0b01) +#define TCR_SHOS (0b10) +#define TCR_SHIS (0b11) + +#define TCR_TG1(g) (((g) & 0b11) << 30) +#define TCR_TG0(g) (((g) & 0b11) << 14) + +#define TCR_T1SZ(sz) (((sz) & 0b111111) << 16) +#define TCR_T0SZ(sz) (((sz) & 0b111111)) + +#define TCR_EPD1 (1UL << 23) +#define TCR_EPD0 (1UL << 7) +#define TCR_A1 (1UL << 22) + +#endif /* __LUNAIX_AA64_MSRS_H */ diff --git a/lunaix-os/scripts/build-tools/integration/lunamenu.py b/lunaix-os/scripts/build-tools/integration/lunamenu.py index c8d0730..d22ed2a 100644 --- a/lunaix-os/scripts/build-tools/integration/lunamenu.py +++ b/lunaix-os/scripts/build-tools/integration/lunamenu.py @@ -118,6 +118,7 @@ class MainMenuContext(tui.TuiContext): t = menu.create_title(self, "Lunaix Kernel Configuration" + suffix) t2 = menu.create_title(self, repo_info) + t2.set_local_pos(2, 0) t2.set_alignment(Alignment.BOT | Alignment.RIGHT) root.add(t)