From 287a5f7ae6a3bec3d679a5de394e915b56c7367d Mon Sep 17 00:00:00 2001 From: Minep Date: Sun, 13 Mar 2022 15:36:13 +0000 Subject: [PATCH] minor adjustments --- lunaix-os/hal/acpi/acpi.c | 6 +++--- lunaix-os/hal/apic.c | 3 --- lunaix-os/includes/hal/acpi/acpi.h | 6 +++--- lunaix-os/includes/hal/acpi/madt.h | 2 +- lunaix-os/includes/lunaix/timer.h | 2 +- lunaix-os/kernel/k_init.c | 2 +- lunaix-os/kernel/kprintf.c | 2 +- lunaix-os/kernel/timer.c | 16 +++++++++------- 8 files changed, 19 insertions(+), 20 deletions(-) diff --git a/lunaix-os/hal/acpi/acpi.c b/lunaix-os/hal/acpi/acpi.c index a37466a..a998278 100644 --- a/lunaix-os/hal/acpi/acpi.c +++ b/lunaix-os/hal/acpi/acpi.c @@ -115,11 +115,11 @@ acpi_locate_rsdp(multiboot_info_t* mb_info) #else // You know what, I just search the entire 1MiB for Celestia's sake. uint8_t* mem_start = 0x4000; - for (size_t j = 0; j < 0x100000; j += 16) { - uint32_t sig_low = *((uint32_t*)(mem_start + j)); + for (; mem_start < 0x100000; mem_start += 16) { + uint32_t sig_low = *((uint32_t*)(mem_start)); // uint32_t sig_high = *((uint32_t*)(mem_start+j) + 1); if (sig_low == ACPI_RSDP_SIG_L) { - rsdp = (acpi_rsdp_t*)(mem_start + j); + rsdp = (acpi_rsdp_t*)(mem_start); break; } } diff --git a/lunaix-os/hal/apic.c b/lunaix-os/hal/apic.c index 32bfed5..30951ef 100644 --- a/lunaix-os/hal/apic.c +++ b/lunaix-os/hal/apic.c @@ -20,9 +20,6 @@ LOG_MODULE("APIC") -void -apic_setup_timer(); - void apic_setup_lvts(); diff --git a/lunaix-os/includes/hal/acpi/acpi.h b/lunaix-os/includes/hal/acpi/acpi.h index 8926244..326a8d0 100644 --- a/lunaix-os/includes/hal/acpi/acpi.h +++ b/lunaix-os/includes/hal/acpi/acpi.h @@ -9,15 +9,15 @@ #include "madt.h" #define ACPI_RSDP_SIG_L 0x20445352 // 'RSD ' -#define ACPI_RSDP_SIG_H 0x20525450 // 'PTR ' +#define ACPI_RSDP_SIG_H 0x20525450 // 'PTR ' -#define ACPI_MADT_SIG 0x43495041 // 'APIC' +#define ACPI_MADT_SIG 0x43495041 // 'APIC' typedef struct { uint32_t signature_l; uint32_t signature_h; uint8_t chksum; - uint8_t oem_id[6]; + char oem_id[6]; // Revision uint8_t rev; acpi_rsdt_t* rsdt; diff --git a/lunaix-os/includes/hal/acpi/madt.h b/lunaix-os/includes/hal/acpi/madt.h index ca75d08..72aca46 100644 --- a/lunaix-os/includes/hal/acpi/madt.h +++ b/lunaix-os/includes/hal/acpi/madt.h @@ -83,6 +83,6 @@ typedef struct acpi_apic_t* apic; acpi_ioapic_t* ioapic; acpi_intso_t** irq_exception; -} acpi_madt_toc_t; +} __attribute__((packed)) acpi_madt_toc_t; #endif /* __LUNAIX_ACPI_MADT_H */ diff --git a/lunaix-os/includes/lunaix/timer.h b/lunaix-os/includes/lunaix/timer.h index 5c40696..0c65ffd 100644 --- a/lunaix-os/includes/lunaix/timer.h +++ b/lunaix-os/includes/lunaix/timer.h @@ -4,7 +4,7 @@ #include #include -#define SYS_TIMER_FREQUENCY_HZ 2048UL +#define SYS_TIMER_FREQUENCY_HZ 2048 #define TIMER_MODE_PERIODIC 0x1 diff --git a/lunaix-os/kernel/k_init.c b/lunaix-os/kernel/k_init.c index 5e6cc99..ce97b6e 100644 --- a/lunaix-os/kernel/k_init.c +++ b/lunaix-os/kernel/k_init.c @@ -95,8 +95,8 @@ _kernel_post_init() { vmm_set_mapping(APIC_BASE_VADDR, __APIC_BASE_PADDR, PG_PREM_RW); vmm_set_mapping(IOAPIC_BASE_VADDR, ioapic_addr, PG_PREM_RW); - ioapic_init(); apic_init(); + ioapic_init(); timer_init(SYS_TIMER_FREQUENCY_HZ); for (size_t i = 256; i < hhk_init_pg_count; i++) { diff --git a/lunaix-os/kernel/kprintf.c b/lunaix-os/kernel/kprintf.c index 3bae867..425fc22 100644 --- a/lunaix-os/kernel/kprintf.c +++ b/lunaix-os/kernel/kprintf.c @@ -26,7 +26,7 @@ __kprintf(const char* component, const char* fmt, va_list args) { break; case '1': tty_set_theme(VGA_COLOR_BROWN, current_theme >> 12); - snprintf(expanded_fmt, MAX_XFMT_SIZE, "[%s] (%s) %s", "INFO", component, fmt); + snprintf(expanded_fmt, MAX_XFMT_SIZE, "[%s] (%s) %s", "WARN", component, fmt); break; case '2': tty_set_theme(VGA_COLOR_LIGHT_RED, current_theme >> 12); diff --git a/lunaix-os/kernel/timer.c b/lunaix-os/kernel/timer.c index bf3e699..3a261ac 100644 --- a/lunaix-os/kernel/timer.c +++ b/lunaix-os/kernel/timer.c @@ -76,11 +76,13 @@ timer_init(uint32_t frequency) Timer calibration process - measure the APIC timer base frequency step 1: setup a temporary isr for RTC timer which trigger at each tick - (1024Hz) step 2: setup a temporary isr for #APIC_TIMER_IV step 3: setup - the divider, APIC_TIMER_DCR step 4: Startup RTC timer step 5: Write a - large value, v, to APIC_TIMER_ICR to start APIC timer (this must be - followed immediately after step 4) step 6: issue a write to EOI and clean - up. + (1024Hz) + step 2: setup a temporary isr for #APIC_TIMER_IV + step 3: setup the divider, APIC_TIMER_DCR + step 4: Startup RTC timer + step 5: Write a large value, v, to APIC_TIMER_ICR to start APIC timer (this must be + followed immediately after step 4) + step 6: issue a write to EOI and clean up. When the APIC ICR counting down to 0 #APIC_TIMER_IV triggered, save the rtc timer's counter, k, and disable RTC timer immediately (although the @@ -147,7 +149,7 @@ timer_run(uint32_t ticks, void (*callback)(void*), void* payload, uint8_t flags) timer->payload = payload; timer->flags = flags; - llist_append(timer_ctx->active_timers, timer); + llist_append(timer_ctx->active_timers, &timer->link); return 1; } @@ -169,7 +171,7 @@ timer_update(const isr_param* param) if (pos->flags & TIMER_MODE_PERIODIC) { pos->counter = pos->deadline; } else { - llist_delete(pos); + llist_delete(&pos->link); lxfree(pos); } } -- 2.27.0