From 423c98c95abf756e6982c51fd7757dcb67f3f9ea Mon Sep 17 00:00:00 2001 From: Minep Date: Mon, 27 Jun 2022 19:09:49 +0100 Subject: [PATCH 1/1] feat: MSI capability detection. refactor: better interfacing and more compact pci device struct. --- lunaix-os/hal/pci.c | 104 +++++++++++++++++++++++------------ lunaix-os/includes/hal/pci.h | 49 ++++++++++------- 2 files changed, 98 insertions(+), 55 deletions(-) diff --git a/lunaix-os/hal/pci.c b/lunaix-os/hal/pci.c index 8bc35ce..90011c6 100644 --- a/lunaix-os/hal/pci.c +++ b/lunaix-os/hal/pci.c @@ -6,19 +6,21 @@ LOG_MODULE("PCI") static struct llist_header pci_devices; +void +pci_probe_msi_info(struct pci_device* device); + void pci_probe_device(int bus, int dev, int funct) { - pci_reg_t reg1 = pci_read_cspace(bus, dev, funct, 0); - uint32_t vendor = reg1 & 0xffff; - pci_reg_t dev_id = reg1 >> 16; + uint32_t base = PCI_ADDRESS(bus, dev, funct); + pci_reg_t reg1 = pci_read_cspace(base, 0); // Vendor=0xffff则表示设备不存在 - if (vendor == PCI_VENDOR_INVLD) { + if (PCI_DEV_VENDOR(reg1) == PCI_VENDOR_INVLD) { return; } - pci_reg_t hdr_type = pci_read_cspace(bus, dev, funct, 3); + pci_reg_t hdr_type = pci_read_cspace(base, 0xc); hdr_type = (hdr_type >> 16) & 0xff; if ((hdr_type & 0x80)) { @@ -34,24 +36,16 @@ pci_probe_device(int bus, int dev, int funct) return; } - pci_reg_t intr = pci_read_cspace(bus, dev, funct, 15); - pci_reg_t class = pci_read_cspace(bus, dev, funct, 2) >> 8; + pci_reg_t intr = pci_read_cspace(base, 0x3c); + pci_reg_t class = pci_read_cspace(base, 0x8); struct pci_device* device = lxmalloc(sizeof(struct pci_device)); - *device = (struct pci_device){ .bus = bus, - .dev = dev, - .function = funct, - .class_code = class, - .vendor = vendor, - .deviceId = dev_id, - .type = hdr_type, - .intr_line = intr & 0xff, - .intr_pintype = (intr >> 8) & 0xff }; - - // 读取设备的内存映射的寄存器的基地址 - for (int i = 0; i < 6; i++) { - device->bars[i] = pci_read_cspace(bus, dev, funct, 4 + i); - } + *device = (struct pci_device){ .cspace_base = base, + .class_info = class, + .device_info = reg1, + .intr_info = intr }; + + pci_probe_msi_info(device); llist_append(&pci_devices, &device->dev_chain); } @@ -68,6 +62,31 @@ pci_probe() } } +void +pci_probe_msi_info(struct pci_device* device) +{ + pci_reg_t status = + pci_read_cspace(device->cspace_base, PCI_REG_STATUS_CMD) >> 16; + + if (!(status & 0x10)) { + device->msi_loc = 0; + return; + } + + pci_reg_t cap_ptr = pci_read_cspace(device->cspace_base, 0x34) & 0xff; + uint32_t cap_hdr; + + while (cap_ptr) { + cap_hdr = pci_read_cspace(device->cspace_base, cap_ptr); + if ((cap_hdr & 0xff) == 0x5) { + // MSI + device->msi_loc = cap_ptr; + return; + } + cap_ptr = (cap_hdr >> 8) & 0xff; + } +} + void pci_print_device() { @@ -75,28 +94,45 @@ pci_print_device() llist_for_each(pos, n, &pci_devices, dev_chain) { kprintf(KINFO "(B%xh:D%xh:F%xh) Dev %x:%x, Class 0x%x\n", - pos->bus, - pos->dev, - pos->function, - pos->vendor, - pos->deviceId, - pos->class_code); - - for (int i = 0; i < 6; i++) { - kprintf(KINFO "\t BAR#%d: %p\n", i, pos->bars[i]); + PCI_BUS_NUM(pos->cspace_base), + PCI_SLOT_NUM(pos->cspace_base), + PCI_FUNCT_NUM(pos->cspace_base), + PCI_DEV_VENDOR(pos->device_info), + PCI_DEV_DEVID(pos->device_info), + PCI_DEV_CLASS(pos->class_info)); + + kprintf(KINFO "\t IRQ: %d, INT#x: %d\n", + PCI_INTR_IRQ(pos->intr_info), + PCI_INTR_PIN(pos->intr_info)); + + if (pos->msi_loc) { + kprintf(KINFO "\t MSI supported (@%xh)\n", pos->msi_loc); } - kprintf( - KINFO "\t IRQ: %d, INT#x: %d\n\n", pos->intr_line, pos->intr_pintype); } } struct pci_device* -pci_get_device(uint16_t vendorId, uint16_t deviceId) +pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId) +{ + uint32_t dev_info = vendorId | (deviceId << 16); + struct pci_device *pos, *n; + llist_for_each(pos, n, &pci_devices, dev_chain) + { + if (pos->device_info == dev_info) { + return pos; + } + } + + return NULL; +} + +struct pci_device* +pci_get_device_by_class(uint32_t class) { struct pci_device *pos, *n; llist_for_each(pos, n, &pci_devices, dev_chain) { - if (pos->vendor == vendorId && pos->deviceId == deviceId) { + if (PCI_DEV_CLASS(pos->class_info) == class) { return pos; } } diff --git a/lunaix-os/includes/hal/pci.h b/lunaix-os/includes/hal/pci.h index 3e421ee..bd20359 100644 --- a/lunaix-os/includes/hal/pci.h +++ b/lunaix-os/includes/hal/pci.h @@ -13,13 +13,23 @@ #define PCI_VENDOR_INVLD 0xffff -#define PCI_REG_VENDER 0x0 -#define PCI_REG_DEV 0x1 -#define PCI_REG_HDRTYPE 0x7 - -#define PCI_ADDRESS(bus, dev, funct, reg) \ +#define PCI_REG_VENDOR_DEV 0 +#define PCI_REG_STATUS_CMD 0x4 +#define PCI_REG_BAR(offset) (0x10 + (offset)*4) + +#define PCI_DEV_VENDOR(x) ((x)&0xffff) +#define PCI_DEV_DEVID(x) ((x) >> 16) +#define PCI_INTR_IRQ(x) ((x)&0xff) +#define PCI_INTR_PIN(x) (((x)&0xff00) >> 8) +#define PCI_DEV_CLASS(x) ((x) >> 8) +#define PCI_DEV_REV(x) (((x)&0xff)) +#define PCI_BUS_NUM(x) ((x >> 16) & 0xff) +#define PCI_SLOT_NUM(x) ((x >> 11) & 0x1f) +#define PCI_FUNCT_NUM(x) ((x >> 8) & 0x7) + +#define PCI_ADDRESS(bus, dev, funct) \ (((bus)&0xff) << 16) | (((dev)&0xff) << 11) | (((funct)&0xff) << 8) | \ - (((reg)&0xff) << 2) | 0x80000000 + 0x80000000 typedef unsigned int pci_reg_t; @@ -29,32 +39,27 @@ typedef unsigned int pci_reg_t; struct pci_device { struct llist_header dev_chain; - uint16_t vendor; - uint16_t deviceId; - uint32_t class_code; - uint8_t bus; - uint8_t dev; - uint8_t function; - uint8_t type; - uint8_t intr_line; - uint8_t intr_pintype; - uint32_t bars[6]; + uint32_t device_info; + uint32_t class_info; + uint32_t cspace_base; + uint32_t msi_loc; + uint16_t intr_info; }; // PCI Configuration Space (C-Space) r/w: // Refer to "PCI Local Bus Specification, Rev.3, Section 3.2.2.3.2" inline pci_reg_t -pci_read_cspace(int bus, int dev, int funct, int reg) +pci_read_cspace(uint32_t base, int offset) { - io_outl(PCI_CONFIG_ADDR, PCI_ADDRESS(bus, dev, funct, reg)); + io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3)); return io_inl(PCI_CONFIG_DATA); } inline void -pci_write_cspace(int bus, int dev, int funct, int reg, pci_reg_t data) +pci_write_cspace(uint32_t base, int offset, pci_reg_t data) { - io_outl(PCI_CONFIG_ADDR, PCI_ADDRESS(bus, dev, funct, reg)); + io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3)); io_outl(PCI_CONFIG_DATA, data); } @@ -67,7 +72,9 @@ pci_init(); void pci_print_device(); +struct pci_device* pci_get_device_by_class(uint32_t class); + struct pci_device* -pci_get_device(uint16_t vendorId, uint16_t deviceId); +pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId); #endif /* __LUNAIX_PCI_H */ -- 2.27.0