lunaix-os/arch/x86/hal/mc146818a.c

   1 /**
   2  * @file rtc.c
   3  * @author Lunaixsky
   4  * @brief RTC & CMOS abstraction. Reference: MC146818A & Intel Series 500 PCH
   5  * datasheet
   6  * @version 0.1
   7  * @date 2022-03-07
   8  *
   9  * @copyright Copyright (c) 2022
  10  *
  11  */
  12
  13 #include <lunaix/mm/valloc.h>
  14 #include <lunaix/status.h>
  15 #include <lunaix/hart_state.h>
  16
  17 #include <hal/hwrtc.h>
  18
  19 #include <klibc/string.h>
  20
  21 #include <asm/x86_isrm.h>
  22 #include <asm/x86_pmio.h>
  23
  24 #define RTC_INDEX_PORT 0x70
  25 #define RTC_TARGET_PORT 0x71
  26
  27 #define RTC_CURRENT_CENTRY 20
  28
  29 #define RTC_REG_YRS 0x9
  30 #define RTC_REG_MTH 0x8
  31 #define RTC_REG_DAY 0x7
  32 #define RTC_REG_WDY 0x6
  33 #define RTC_REG_HRS 0x4
  34 #define RTC_REG_MIN 0x2
  35 #define RTC_REG_SEC 0x0
  36
  37 #define RTC_REG_A 0xA
  38 #define RTC_REG_B 0xB
  39 #define RTC_REG_C 0xC
  40 #define RTC_REG_D 0xD
  41
  42 #define RTC_SET 0x80
  43 #define RTC_BIN (1 << 2)
  44 #define RTC_HOURFORM24 (1 << 1)
  45
  46 #define RTC_BIN_ENCODED(reg) (reg & 0x04)
  47 #define RTC_24HRS_ENCODED(reg) (reg & 0x02)
  48
  49 #define RTC_TIMER_BASE_FREQUENCY 1024
  50 #define RTC_TIMER_ON 0x40
  51
  52 #define RTC_FREQUENCY_1024HZ 0b110
  53 #define RTC_DIVIDER_33KHZ (0b010 << 4)
  54
  55 #define PC_AT_IRQ_RTC                   8
  56
  57 struct mc146818
  58 {
  59     struct hwrtc_potens* rtc_context;
  60     u32_t rtc_iv;
  61 };
  62
  63 #define rtc_state(data) ((struct mc146818*)(data))
  64
  65 static inline u8_t
  66 rtc_read_reg(u8_t reg_selector)
  67 {
  68     port_wrbyte(RTC_INDEX_PORT, reg_selector);
  69     return port_rdbyte(RTC_TARGET_PORT);
  70 }
  71
  72 static inline void
  73 rtc_write_reg(u8_t reg_selector, u8_t val)
  74 {
  75     port_wrbyte(RTC_INDEX_PORT, reg_selector);
  76     port_wrbyte(RTC_TARGET_PORT, val);
  77 }
  78
  79 static inline void
  80 rtc_enable_timer()
  81 {
  82     u8_t regB = rtc_read_reg(RTC_REG_B);
  83     rtc_write_reg(RTC_REG_B, regB | RTC_TIMER_ON);
  84 }
  85
  86 static inline void
  87 rtc_disable_timer()
  88 {
  89     u8_t regB = rtc_read_reg(RTC_REG_B);
  90     rtc_write_reg(RTC_REG_B, regB & ~RTC_TIMER_ON);
  91 }
  92
  93 static void
  94 rtc_getwalltime(struct hwrtc_potens* rtc, datetime_t* datetime)
  95 {
  96     datetime_t current;
  97
  98     do {
  99         while (rtc_read_reg(RTC_REG_A) & 0x80)
 100             ;
 101         memcpy(&current, datetime, sizeof(datetime_t));
 102
 103         datetime->year = rtc_read_reg(RTC_REG_YRS);
 104         datetime->month = rtc_read_reg(RTC_REG_MTH);
 105         datetime->day = rtc_read_reg(RTC_REG_DAY);
 106         datetime->weekday = rtc_read_reg(RTC_REG_WDY);
 107         datetime->hour = rtc_read_reg(RTC_REG_HRS);
 108         datetime->minute = rtc_read_reg(RTC_REG_MIN);
 109         datetime->second = rtc_read_reg(RTC_REG_SEC);
 110     } while (!datatime_eq(datetime, &current));
 111
 112     datetime->year += RTC_CURRENT_CENTRY * 100;
 113 }
 114
 115 static void
 116 rtc_setwalltime(struct hwrtc_potens* rtc, datetime_t* datetime)
 117 {
 118     u8_t reg = rtc_read_reg(RTC_REG_B);
 119     reg = reg & ~RTC_SET;
 120
 121     rtc_write_reg(RTC_REG_B, reg | RTC_SET);
 122
 123     rtc_write_reg(RTC_REG_YRS, datetime->year - RTC_CURRENT_CENTRY * 100);
 124     rtc_write_reg(RTC_REG_MTH, datetime->month);
 125     rtc_write_reg(RTC_REG_DAY, datetime->day);
 126     rtc_write_reg(RTC_REG_WDY, datetime->weekday);
 127     rtc_write_reg(RTC_REG_HRS, datetime->hour);
 128     rtc_write_reg(RTC_REG_MIN, datetime->minute);
 129     rtc_write_reg(RTC_REG_SEC, datetime->second);
 130
 131     rtc_write_reg(RTC_REG_B, reg & ~RTC_SET);
 132 }
 133
 134 static void
 135 __rtc_tick(const struct hart_state* hstate)
 136 {
 137     struct mc146818* state = (struct mc146818*)isrm_get_payload(hstate);
 138
 139     state->rtc_context->live++;
 140
 141     (void)rtc_read_reg(RTC_REG_C);
 142 }
 143
 144 static void
 145 rtc_set_proactive(struct hwrtc_potens* pot, bool proactive)
 146 {
 147     if (proactive) {
 148         pot->state = 0;
 149         rtc_enable_timer();
 150     }
 151     else {
 152         pot->state = RTC_STATE_MASKED;
 153         rtc_disable_timer();
 154     }
 155 }
 156
 157 static int
 158 rtc_chfreq(struct hwrtc_potens* rtc, int freq)
 159 {
 160     return ENOTSUP;
 161 }
 162
 163 static int
 164 __rtc_calibrate(struct hwrtc_potens* pot)
 165 {
 166     struct mc146818* state;
 167
 168     u8_t reg = rtc_read_reg(RTC_REG_A);
 169     reg = (reg & ~0x7f) | RTC_FREQUENCY_1024HZ | RTC_DIVIDER_33KHZ;
 170     rtc_write_reg(RTC_REG_A, reg);
 171
 172     reg = RTC_BIN | RTC_HOURFORM24;
 173     rtc_write_reg(RTC_REG_B, reg);
 174
 175     // Make sure the rtc timer is disabled by default
 176     rtc_disable_timer();
 177
 178     pot->base_freq = RTC_TIMER_BASE_FREQUENCY;
 179
 180     state = (struct mc146818*)potens_dev(pot)->underlay;
 181     state->rtc_iv = isrm_bindirq(PC_AT_IRQ_RTC, __rtc_tick);
 182     isrm_set_payload(state->rtc_iv, __ptr(state));
 183
 184     return 0;
 185 }
 186
 187 static struct hwrtc_potens_ops ops = {
 188     .get_walltime  = rtc_getwalltime,
 189     .set_walltime  = rtc_setwalltime,
 190     .set_proactive = rtc_set_proactive,
 191     .chfreq = rtc_chfreq,
 192     .calibrate = __rtc_calibrate
 193 };
 194
 195 static int
 196 rtc_load(struct device_def* devdef)
 197 {
 198     struct device* dev;
 199     struct mc146818* state;
 200     struct hwrtc_potens* pot;
 201
 202     state = valloc(sizeof(struct mc146818));
 203     dev = device_allocsys(NULL, state);
 204
 205     pot = hwrtc_attach_potens(dev, &ops);
 206     if (!pot) {
 207         return 1;
 208     }
 209
 210     pot->state = RTC_STATE_MASKED;
 211     state->rtc_context = pot;
 212
 213     register_device(dev, &devdef->class, "mc146818");
 214
 215     return 0;
 216 }
 217
 218 static struct device_def devrtc_mc146818 = {
 219     def_device_class(INTEL, TIME, RTC),
 220     def_device_name("x86 legacy RTC"),
 221     def_on_load(rtc_load)
 222 };
 223 EXPORT_DEVICE(mc146818, &devrtc_mc146818, load_sysconf);