5 #include <lunaix/ds/llist.h>
7 #define PCI_CONFIG_ADDR 0xcf8
8 #define PCI_CONFIG_DATA 0xcfc
11 #define PCI_TPCIBRIDGE 0x1
12 #define PCI_TCARDBRIDGE 0x2
14 #define PCI_VENDOR_INVLD 0xffff
16 #define PCI_REG_VENDOR_DEV 0
17 #define PCI_REG_STATUS_CMD 0x4
18 #define PCI_REG_BAR(offset) (0x10 + (offset)*4)
20 #define PCI_DEV_VENDOR(x) ((x)&0xffff)
21 #define PCI_DEV_DEVID(x) ((x) >> 16)
22 #define PCI_INTR_IRQ(x) ((x)&0xff)
23 #define PCI_INTR_PIN(x) (((x)&0xff00) >> 8)
24 #define PCI_DEV_CLASS(x) ((x) >> 8)
25 #define PCI_DEV_REV(x) (((x)&0xff))
26 #define PCI_BUS_NUM(x) ((x >> 16) & 0xff)
27 #define PCI_SLOT_NUM(x) ((x >> 11) & 0x1f)
28 #define PCI_FUNCT_NUM(x) ((x >> 8) & 0x7)
30 #define PCI_ADDRESS(bus, dev, funct) \
31 (((bus)&0xff) << 16) | (((dev)&0xff) << 11) | (((funct)&0xff) << 8) | \
34 typedef unsigned int pci_reg_t;
36 // PCI device header format
37 // Ref: "PCI Local Bus Specification, Rev.3, Section 6.1"
41 struct llist_header dev_chain;
49 // PCI Configuration Space (C-Space) r/w:
50 // Refer to "PCI Local Bus Specification, Rev.3, Section 3.2.2.3.2"
53 pci_read_cspace(uint32_t base, int offset)
55 io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
56 return io_inl(PCI_CONFIG_DATA);
60 pci_write_cspace(uint32_t base, int offset, pci_reg_t data)
62 io_outl(PCI_CONFIG_ADDR, base | (offset & ~0x3));
63 io_outl(PCI_CONFIG_DATA, data);
75 struct pci_device* pci_get_device_by_class(uint32_t class);
78 pci_get_device_by_id(uint16_t vendorId, uint16_t deviceId);
80 #endif /* __LUNAIX_PCI_H */