add basic exception model and context switching for aarch64
[lunaix-os.git] / lunaix-os / arch / aarch64 / includes / asm / aa64_exception.h
1 #ifndef __LUNAIX_AA64_ESR_H
2 #define __LUNAIX_AA64_ESR_H
3
4 #ifdef __ASM__
5
6 #define EXCEPTION_SYNC      0
7 #define EXCEPTION_IFQ       1
8 #define EXCEPTION_IRQ       2
9 #define EXCEPTION_SERR      3
10
11 #else
12
13 #include <lunaix/bits.h>
14 #include <lunaix/types.h>
15
16 #define ESR_ISS2            BITS(55, 32)
17 #define ESR_EC              BITS(31, 26)
18 #define ESR_IL              BIT(25)
19 #define ESR_ISS             BITS(24,  0)
20
21 #define EC_UNKNOWN          0b000000
22 #define EC_WF               0b000001
23 #define EC_SIMD             0b000111
24 #define EC_LS64             0b001010
25 #define EC_BTI              0b001101
26 #define EC_EXEC_STATE       0b001110
27 #define EC_SYS_INST         0b011000
28
29 #define EC_I_ABORT          0b100000
30 #define EC_I_ABORT_EL       0b100001
31
32 #define EC_D_ABORT          0b100100
33 #define EC_D_ABORT_EL       0b100101
34
35 #define EC_PC_ALIGN         0b100010
36 #define EC_SP_ALIGN         0b100110
37
38 #define EC_SERROR           0b101111
39
40 static inline bool
41 esr_inst32(reg_t esr)
42 {
43     return !!BITS_GET(esr, ESR_IL);
44 }
45
46 static inline unsigned int
47 esr_ec(reg_t esr)
48 {
49     return (unsigned int)BITS_GET(esr, ESR_EC);
50 }
51
52 static inline reg_t
53 esr_iss(reg_t esr)
54 {
55     return (reg_t)BITS_GET(esr, ESR_ISS);
56 }
57
58 #endif /* !__ASM__ */
59 #endif /* __LUNAIX_AA64_ESR_H */